Makefile.am | 10 autogen.sh | 2 configure.ac | 69 exynos/Makefile.am | 22 exynos/exynos_drm.c | 396 +++ exynos/exynos_drm.h | 146 + exynos/exynos_drmif.h | 88 exynos/libdrm_exynos.pc.in | 11 include/drm/Makefile.am | 1 include/drm/drm.h | 20 include/drm/drm_fourcc.h | 130 + include/drm/drm_mode.h | 89 include/drm/i915_drm.h | 79 include/drm/radeon_drm.h | 24 intel/.gitignore | 1 intel/Makefile.am | 37 intel/intel_aub.h | 123 + intel/intel_bufmgr.c | 52 intel/intel_bufmgr.h | 56 intel/intel_bufmgr_gem.c | 1053 +++++++- intel/intel_bufmgr_priv.h | 5 intel/intel_chipset.h | 132 - intel/intel_debug.h | 44 intel/intel_decode.c | 3977 +++++++++++++++++++++++++++++++++ intel/test_decode.c | 191 + intel/tests/.gitignore | 1 intel/tests/gen4-3d.batch |binary intel/tests/gen4-3d.batch-ref.txt | 488 ++++ intel/tests/gen4-3d.batch.sh | 1 intel/tests/gen5-3d.batch |binary intel/tests/gen5-3d.batch-ref.txt | 512 ++++ intel/tests/gen5-3d.batch.sh | 1 intel/tests/gen6-3d.batch |binary intel/tests/gen6-3d.batch-ref.txt | 990 ++++++++ intel/tests/gen6-3d.batch.sh | 1 intel/tests/gen7-2d-copy.batch |binary intel/tests/gen7-2d-copy.batch-ref.txt | 14 intel/tests/gen7-2d-copy.batch.sh | 1 intel/tests/gen7-3d.batch |binary intel/tests/gen7-3d.batch-ref.txt | 212 + intel/tests/gen7-3d.batch.sh | 1 intel/tests/gm45-3d.batch |binary intel/tests/gm45-3d.batch-ref.txt | 488 ++++ intel/tests/gm45-3d.batch.sh | 1 intel/tests/test-batch.sh | 20 libdrm_lists.h | 29 libkms/dumb.c | 3 nouveau/Makefile.am | 36 nouveau/abi16.c | 195 + nouveau/bufctx.c | 170 + nouveau/libdrm_nouveau.pc.in | 2 nouveau/nouveau.c | 492 ++++ nouveau/nouveau.h | 212 + nouveau/nouveau_bo.c | 549 ---- nouveau/nouveau_bo.h | 104 nouveau/nouveau_channel.c | 142 - nouveau/nouveau_channel.h | 57 nouveau/nouveau_device.c | 196 - nouveau/nouveau_device.h | 33 nouveau/nouveau_drmif.h | 58 nouveau/nouveau_grobj.c | 147 - nouveau/nouveau_grobj.h | 48 nouveau/nouveau_notifier.c | 148 - nouveau/nouveau_notifier.h | 63 nouveau/nouveau_private.h | 136 - nouveau/nouveau_pushbuf.c | 343 -- nouveau/nouveau_pushbuf.h | 162 - nouveau/nouveau_reloc.c | 154 - nouveau/nouveau_reloc.h | 32 nouveau/nouveau_resource.c | 124 - nouveau/nouveau_resource.h | 51 nouveau/nv04_pushbuf.h | 66 nouveau/nvc0_pushbuf.h | 92 nouveau/private.h | 122 + nouveau/pushbuf.c | 773 ++++++ omap/Makefile.am | 22 omap/libdrm_omap.pc.in | 11 omap/omap_drm.c | 331 ++ omap/omap_drm.h | 134 + omap/omap_drmif.h | 62 radeon/Makefile.am | 5 radeon/r600_pci_ids.h | 353 ++ radeon/radeon_cs_space.c | 15 radeon/radeon_surface.c | 1064 ++++++++ radeon/radeon_surface.h | 114 tests/Makefile.am | 4 tests/drmtest.c | 13 tests/gem_flink.c | 7 tests/modeprint/modeprint.c | 7 tests/modetest/modetest.c | 563 ++++ tests/radeon/Makefile.am | 14 tests/radeon/list.h | 137 + tests/radeon/radeon_ttm.c | 75 tests/radeon/rbo.c | 171 + tests/radeon/rbo.h | 50 tests/vbltest/vbltest.c | 22 xf86drm.c | 8 xf86drm.h | 8 xf86drmMode.c | 257 ++ xf86drmMode.h | 61 100 files changed, 14778 insertions(+), 2958 deletions(-)
New commits: commit 1b1a4f0a779f7ab2ba5673b9c9fe2a37047fe765 Author: Ben Widawsky <[email protected]> Date: Fri Jun 29 11:08:05 2012 -0700 configure: bump version for release Signed-off-by: Ben Widawsky <[email protected]> diff --git a/configure.ac b/configure.ac index 1e23b36..a1c8c69 100644 --- a/configure.ac +++ b/configure.ac @@ -20,7 +20,7 @@ AC_PREREQ([2.63]) AC_INIT([libdrm], - [2.4.36], + [2.4.37], [https://bugs.freedesktop.org/enter_bug.cgi?product=DRI], [libdrm]) commit f7210fa4ecf6a5456aa5a6bcc0584d38b2c8449e Author: Ben Widawsky <[email protected]> Date: Fri Jan 13 11:31:52 2012 -0800 intel/context: create/destroy implementation Add relevant code to set up minimal state and call the appropriate kernel IOCTLs. This was missed in the previous cherry-picking for 2.3.36. Signed-off-by: Ben Widawsky <[email protected]> diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c index 485308b..a957c28 100644 --- a/intel/intel_bufmgr_gem.c +++ b/intel/intel_bufmgr_gem.c @@ -2840,6 +2840,51 @@ drm_intel_bufmgr_gem_set_aub_dump(drm_intel_bufmgr *bufmgr, int enable) } } +drm_intel_context * +drm_intel_gem_context_create(drm_intel_bufmgr *bufmgr) +{ + drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr; + struct drm_i915_gem_context_create create; + drm_i915_getparam_t gp; + drm_intel_context *context = NULL; + int tmp = 0, ret; + + ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_CONTEXT_CREATE, &create); + if (ret != 0) { + fprintf(stderr, "DRM_IOCTL_I915_GEM_CONTEXT_CREATE failed: %s\n", + strerror(errno)); + return NULL; + } + + context = calloc(1, sizeof(*context)); + context->ctx_id = create.ctx_id; + context->bufmgr = bufmgr; + + return context; +} + +void +drm_intel_gem_context_destroy(drm_intel_context *ctx) +{ + drm_intel_bufmgr_gem *bufmgr_gem; + struct drm_i915_gem_context_destroy destroy; + int ret; + + if (ctx == NULL) + return; + + bufmgr_gem = (drm_intel_bufmgr_gem *)ctx->bufmgr; + destroy.ctx_id = ctx->ctx_id; + ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_CONTEXT_DESTROY, + &destroy); + if (ret != 0) + fprintf(stderr, "DRM_IOCTL_I915_GEM_CONTEXT_DESTROY failed: %s\n", + strerror(errno)); + + free(ctx); +} + + /** * Annotate the given bo for use in aub dumping. * commit c0ed9b23ecb48b8301f66d2270e638249709e94e Author: Kristian Høgsberg <[email protected]> Date: Thu Jun 28 10:48:31 2012 -0400 modetest: Dump bit field names diff --git a/tests/modetest/modetest.c b/tests/modetest/modetest.c index dc84cf3..ec3121e 100644 --- a/tests/modetest/modetest.c +++ b/tests/modetest/modetest.c @@ -118,6 +118,49 @@ struct type_name connector_type_names[] = { type_name_fn(connector_type) +#define bit_name_fn(res) \ +char * res##_str(int type) { \ + int i; \ + const char *sep = ""; \ + for (i = 0; i < ARRAY_SIZE(res##_names); i++) { \ + if (type & (1 << i)) { \ + printf("%s%s", sep, res##_names[i]); \ + sep = ", "; \ + } \ + } \ +} + +static const char *mode_type_names[] = { + "builtin", + "clock_c", + "crtc_c", + "preferred", + "default", + "userdef", + "driver", +}; + +bit_name_fn(mode_type) + +static const char *mode_flag_names[] = { + "phsync", + "nhsync", + "pvsync", + "nvsync", + "interlace", + "dblscan", + "csync", + "pcsync", + "ncsync", + "hskew", + "bcast", + "pixmux", + "dblclk", + "clkdiv2" +}; + +bit_name_fn(mode_flag) + void dump_encoders(void) { drmModeEncoder *encoder; @@ -146,7 +189,7 @@ void dump_encoders(void) void dump_mode(drmModeModeInfo *mode) { - printf("\t%s %d %d %d %d %d %d %d %d %d\n", + printf(" %s %d %d %d %d %d %d %d %d %d", mode->name, mode->vrefresh, mode->hdisplay, @@ -157,6 +200,12 @@ void dump_mode(drmModeModeInfo *mode) mode->vsync_start, mode->vsync_end, mode->vtotal); + + printf(" flags: "); + mode_flag_str(mode->flags); + printf("; type: "); + mode_type_str(mode->type); + printf("\n"); } static void commit a7805194b7b91de01b671beeb724584dca69ad68 Author: Ben Widawsky <[email protected]> Date: Wed Jun 27 10:10:53 2012 -0700 intel/decode: fix the reference file for I mistakenly "fixed" a bad decode with commit 7d0a1d5ebbe2c6aecd96eef94b0af038858a0178 Author: Ben Widawsky <[email protected]> Date: Sun Jun 24 20:35:57 2012 -0700 intel/decode: VERTEX_ELEMENT_STATE, 1 means valid However the actual fix is just to update the reference file, and include GEN7 in the decode. Props to Eric Anholt for putting the test in distcheck, or else I wouldn't have caught this. Signed-off-by: Ben Widawsky <[email protected]> diff --git a/configure.ac b/configure.ac index f7bea35..1e23b36 100644 --- a/configure.ac +++ b/configure.ac @@ -20,7 +20,7 @@ AC_PREREQ([2.63]) AC_INIT([libdrm], - [2.4.35], + [2.4.36], [https://bugs.freedesktop.org/enter_bug.cgi?product=DRI], [libdrm]) diff --git a/intel/intel_decode.c b/intel/intel_decode.c index 909ae77..19a8d36 100644 --- a/intel/intel_decode.c +++ b/intel/intel_decode.c @@ -3406,8 +3406,8 @@ decode_3d_965(struct drm_intel_decode *ctx) instr_out(ctx, i, "buffer %d: %svalid, type 0x%04x, " "src offset 0x%04x bytes\n", - data[i] >> (IS_GEN6(devid) ? 26 : 27), - data[i] & (1 << (IS_GEN6(devid) ? 25 : 26)) ? + data[i] >> ((IS_GEN6(devid) || IS_GEN7(devid)) ? 26 : 27), + data[i] & (1 << ((IS_GEN6(devid) || IS_GEN7(devid)) ? 25 : 26)) ? "" : "in", (data[i] >> 16) & 0x1ff, data[i] & 0x07ff); i++; diff --git a/intel/tests/gen7-3d.batch-ref.txt b/intel/tests/gen7-3d.batch-ref.txt index be3c85e..cd2dfc4 100644 --- a/intel/tests/gen7-3d.batch-ref.txt +++ b/intel/tests/gen7-3d.batch-ref.txt @@ -198,9 +198,9 @@ 0x12300314: 0x158c2fff: max index 0x12300318: 0x00000000: mbz 0x1230031c: 0x78090003: 3DSTATE_VERTEX_ELEMENTS -0x12300320: 0x02850000: buffer 0: invalid, type 0x0085, src offset 0x0000 bytes +0x12300320: 0x02850000: buffer 0: valid, type 0x0085, src offset 0x0000 bytes 0x12300324: 0x11230000: (X, Y, 0.0, 1.0), dst offset 0x00 bytes -0x12300328: 0x02400008: buffer 0: invalid, type 0x0040, src offset 0x0008 bytes +0x12300328: 0x02400008: buffer 0: valid, type 0x0040, src offset 0x0008 bytes 0x1230032c: 0x11130000: (X, Y, Z, 1.0), dst offset 0x00 bytes 0x12300330: 0x7b000005: 3DPRIMITIVE: 0x12300334: 0x00000007: quad list sequential commit df5cc69daba12379b5c0bfd49cffd67e7ebedea1 Author: Ben Widawsky <[email protected]> Date: Wed Jun 27 10:19:49 2012 -0700 Revert "intel/decode: VERTEX_ELEMENT_STATE, 1 means valid" This reverts commit 7d0a1d5ebbe2c6aecd96eef94b0af038858a0178. The actual fix diff --git a/intel/intel_decode.c b/intel/intel_decode.c index fa94881..909ae77 100644 --- a/intel/intel_decode.c +++ b/intel/intel_decode.c @@ -3408,7 +3408,7 @@ decode_3d_965(struct drm_intel_decode *ctx) "src offset 0x%04x bytes\n", data[i] >> (IS_GEN6(devid) ? 26 : 27), data[i] & (1 << (IS_GEN6(devid) ? 25 : 26)) ? - "in" : "", (data[i] >> 16) & 0x1ff, + "" : "in", (data[i] >> 16) & 0x1ff, data[i] & 0x07ff); i++; instr_out(ctx, i, "(%s, %s, %s, %s), " commit ee2be4fa7ea8c220291bf122cf3cc9b467d9564d Author: Ben Widawsky <[email protected]> Date: Sun May 27 16:10:51 2012 -0700 intel: add decoding of MI_SET_CONTEXT Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> diff --git a/intel/intel_decode.c b/intel/intel_decode.c index 74dd530..fa94881 100644 --- a/intel/intel_decode.c +++ b/intel/intel_decode.c @@ -139,6 +139,22 @@ instr_out(struct drm_intel_decode *ctx, unsigned int index, } static int +decode_MI_SET_CONTEXT(struct drm_intel_decode *ctx) +{ + uint32_t data = ctx->data[1]; + if (ctx->gen > 7) + return 1; + + instr_out(ctx, 0, "MI_SET_CONTEXT\n"); + instr_out(ctx, 1, "gtt offset = 0x%x%s%s\n", + data & ~0xfff, + data & (1<<1)? ", Force Restore": "", + data & (1<<0)? ", Restore Inhibit": ""); + + return 2; +} + +static int decode_MI_WAIT_FOR_EVENT(struct drm_intel_decode *ctx) { const char *cc_wait; @@ -233,7 +249,7 @@ decode_mi(struct drm_intel_decode *ctx) { 0x00, 0, 1, 1, "MI_NOOP" }, { 0x11, 0x3f, 2, 2, "MI_OVERLAY_FLIP" }, { 0x07, 0, 1, 1, "MI_REPORT_HEAD" }, - { 0x18, 0x3f, 2, 2, "MI_SET_CONTEXT" }, + { 0x18, 0x3f, 2, 2, "MI_SET_CONTEXT", decode_MI_SET_CONTEXT }, { 0x20, 0x3f, 3, 4, "MI_STORE_DATA_IMM" }, { 0x21, 0x3f, 3, 4, "MI_STORE_DATA_INDEX" }, { 0x24, 0x3f, 3, 3, "MI_STORE_REGISTER_MEM" }, commit 3ed38714bd3792ccfc1089dd7bef84ab3dc9697d Author: Ben Widawsky <[email protected]> Date: Sun Mar 18 18:28:28 2012 -0700 intel/context: new execbuf interface for contexts To support this we extract the common execbuf2 functionality to be called with, or without contexts. The context'd execbuf does not support some of the dri1 stuff. Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> diff --git a/intel/intel_bufmgr.h b/intel/intel_bufmgr.h index fedffb5..9b3a483 100644 --- a/intel/intel_bufmgr.h +++ b/intel/intel_bufmgr.h @@ -187,6 +187,11 @@ int drm_intel_get_aperture_sizes(int fd, size_t *mappable, size_t *total); int drm_intel_bufmgr_gem_get_devid(drm_intel_bufmgr *bufmgr); int drm_intel_gem_bo_wait(drm_intel_bo *bo, int64_t timeout_ns); +drm_intel_context *drm_intel_gem_context_create(drm_intel_bufmgr *bufmgr); +void drm_intel_gem_context_destroy(drm_intel_context *ctx); +int drm_intel_gem_bo_context_exec(drm_intel_bo *bo, drm_intel_context *ctx, + int used, unsigned int flags); + /* drm_intel_bufmgr_fake.c */ drm_intel_bufmgr *drm_intel_bufmgr_fake_init(int fd, unsigned long low_offset, diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c index e90f8bd..485308b 100644 --- a/intel/intel_bufmgr_gem.c +++ b/intel/intel_bufmgr_gem.c @@ -2187,9 +2187,9 @@ drm_intel_gem_bo_exec(drm_intel_bo *bo, int used, } static int -drm_intel_gem_bo_mrb_exec2(drm_intel_bo *bo, int used, - drm_clip_rect_t *cliprects, int num_cliprects, int DR4, - unsigned int flags) +do_exec2(drm_intel_bo *bo, int used, drm_intel_context *ctx, + drm_clip_rect_t *cliprects, int num_cliprects, int DR4, + unsigned int flags) { drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr; struct drm_i915_gem_execbuffer2 execbuf; @@ -2231,7 +2231,10 @@ drm_intel_gem_bo_mrb_exec2(drm_intel_bo *bo, int used, execbuf.DR1 = 0; execbuf.DR4 = DR4; execbuf.flags = flags; - execbuf.rsvd1 = 0; + if (ctx == NULL) + i915_execbuffer2_set_context_id(execbuf, 0); + else + i915_execbuffer2_set_context_id(execbuf, ctx->ctx_id); execbuf.rsvd2 = 0; aub_exec(bo, flags, used); @@ -2279,9 +2282,24 @@ drm_intel_gem_bo_exec2(drm_intel_bo *bo, int used, drm_clip_rect_t *cliprects, int num_cliprects, int DR4) { - return drm_intel_gem_bo_mrb_exec2(bo, used, - cliprects, num_cliprects, DR4, - I915_EXEC_RENDER); + return do_exec2(bo, used, NULL, cliprects, num_cliprects, DR4, + I915_EXEC_RENDER); +} + +static int +drm_intel_gem_bo_mrb_exec2(drm_intel_bo *bo, int used, + drm_clip_rect_t *cliprects, int num_cliprects, int DR4, + unsigned int flags) +{ + return do_exec2(bo, used, NULL, cliprects, num_cliprects, DR4, + flags); +} + +int +drm_intel_gem_bo_context_exec(drm_intel_bo *bo, drm_intel_context *ctx, + int used, unsigned int flags) +{ + return do_exec2(bo, used, ctx, NULL, 0, 0, flags); } static int commit b3b123dfb1e81f254fb419d8eef6f63128e5b9c9 Author: Ben Widawsky <[email protected]> Date: Fri Jan 13 11:31:31 2012 -0800 intel/context: Add drm_intel_context type Add an opaque type representing a HW context. Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> diff --git a/intel/intel_bufmgr.h b/intel/intel_bufmgr.h index fa6c4dd..fedffb5 100644 --- a/intel/intel_bufmgr.h +++ b/intel/intel_bufmgr.h @@ -41,6 +41,7 @@ struct drm_clip_rect; typedef struct _drm_intel_bufmgr drm_intel_bufmgr; +typedef struct _drm_intel_context drm_intel_context; typedef struct _drm_intel_bo drm_intel_bo; struct _drm_intel_bo { diff --git a/intel/intel_bufmgr_priv.h b/intel/intel_bufmgr_priv.h index 0b62520..2592d42 100644 --- a/intel/intel_bufmgr_priv.h +++ b/intel/intel_bufmgr_priv.h @@ -280,6 +280,11 @@ struct _drm_intel_bufmgr { int debug; }; +struct _drm_intel_context { + unsigned int ctx_id; + struct _drm_intel_bufmgr *bufmgr; +}; + #define ALIGN(value, alignment) ((value + alignment - 1) & ~(alignment - 1)) #define ROUND_UP_TO(x, y) (((x) + (y) - 1) / (y) * (y)) #define ROUND_UP_TO_MB(x) ROUND_UP_TO((x), 1024*1024) commit a5b2946889471f6075852949f90f660e43b68532 Author: Ben Widawsky <[email protected]> Date: Wed Jun 27 09:52:42 2012 -0700 intel: updated header for contexts Signed-off-by: Ben Widawsky <[email protected]> Reviewed-By: Kenneth Graunke <[email protected]> diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h index 4931107..5c8fabe 100644 --- a/include/drm/i915_drm.h +++ b/include/drm/i915_drm.h @@ -193,6 +193,8 @@ typedef struct _drm_i915_sarea { #define DRM_I915_GET_SPRITE_COLORKEY 0x2a #define DRM_I915_SET_SPRITE_COLORKEY 0x2b #define DRM_I915_GEM_WAIT 0x2c +#define DRM_I915_GEM_CONTEXT_CREATE 0x2d +#define DRM_I915_GEM_CONTEXT_DESTROY 0x2e #define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) #define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH) @@ -237,6 +239,8 @@ typedef struct _drm_i915_sarea { #define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) #define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) #define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait) +#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create) +#define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy) /* Allow drivers to submit batchbuffers directly to hardware, relying * on the security mechanisms provided by hardware. @@ -651,13 +655,19 @@ struct drm_i915_gem_execbuffer2 { #define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6) #define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */ __u64 flags; - __u64 rsvd1; + __u64 rsvd1; /* now used for context info */ __u64 rsvd2; }; /** Resets the SO write offset registers for transform feedback on gen7. */ #define I915_EXEC_GEN7_SOL_RESET (1<<8) +#define I915_EXEC_CONTEXT_ID_MASK (0xffffffff) +#define i915_execbuffer2_set_context_id(eb2, context) \ + (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK +#define i915_execbuffer2_get_context_id(eb2) \ + ((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK) + struct drm_i915_gem_pin { /** Handle of the buffer to be pinned. */ __u32 handle; @@ -889,4 +899,15 @@ struct drm_i915_gem_wait { __s64 timeout_ns; }; +struct drm_i915_gem_context_create { + /* output: id of new context*/ + __u32 ctx_id; + __u32 pad; +}; + +struct drm_i915_gem_context_destroy { + __u32 ctx_id; + __u32 pad; +}; + #endif /* _I915_DRM_H_ */ commit 7d0a1d5ebbe2c6aecd96eef94b0af038858a0178 Author: Ben Widawsky <[email protected]> Date: Sun Jun 24 20:35:57 2012 -0700 intel/decode: VERTEX_ELEMENT_STATE, 1 means valid The logic seemed to be inverse to me. Signed-off-by: Ben Widawsky <[email protected]> diff --git a/intel/intel_decode.c b/intel/intel_decode.c index cf5b3bb..74dd530 100644 --- a/intel/intel_decode.c +++ b/intel/intel_decode.c @@ -3392,7 +3392,7 @@ decode_3d_965(struct drm_intel_decode *ctx) "src offset 0x%04x bytes\n", data[i] >> (IS_GEN6(devid) ? 26 : 27), data[i] & (1 << (IS_GEN6(devid) ? 25 : 26)) ? - "" : "in", (data[i] >> 16) & 0x1ff, + "in" : "", (data[i] >> 16) & 0x1ff, data[i] & 0x07ff); i++; instr_out(ctx, i, "(%s, %s, %s, %s), " commit eeedb0dcc48e02727606d416c28bcb9b86915daa Author: Ben Widawsky <[email protected]> Date: Sun Jun 24 21:53:50 2012 -0700 intel/decode: add sampler state pointers for [HD]S Signed-off-by: Ben Widawsky <[email protected]> diff --git a/intel/intel_decode.c b/intel/intel_decode.c index c9bfee4..cf5b3bb 100644 --- a/intel/intel_decode.c +++ b/intel/intel_decode.c @@ -3188,6 +3188,8 @@ decode_3d_965(struct drm_intel_decode *ctx) { 0x7829, 0x00ff, 2, 2, "3DSTATE_BINDING_TABLE_POINTERS_GS" }, { 0x782a, 0x00ff, 2, 2, "3DSTATE_BINDING_TABLE_POINTERS_PS" }, { 0x782b, 0x00ff, 2, 2, "3DSTATE_SAMPLER_STATE_POINTERS_VS" }, + { 0x782c, 0x00ff, 2, 2, "3DSTATE_SAMPLER_STATE_POINTERS_HS" }, + { 0x782d, 0x00ff, 2, 2, "3DSTATE_SAMPLER_STATE_POINTERS_DS" }, { 0x782e, 0x00ff, 2, 2, "3DSTATE_SAMPLER_STATE_POINTERS_GS" }, { 0x782f, 0x00ff, 2, 2, "3DSTATE_SAMPLER_STATE_POINTERS_PS" }, { 0x7830, 0x00ff, 2, 2, NULL, 7, gen7_3DSTATE_URB_VS }, commit 971c080ac0eb8f0531fe3ebabc5b9e585db992b6 Author: Ben Widawsky <[email protected]> Date: Tue Jun 5 11:30:48 2012 -0700 intel: wait render timeout implementation int drm_intel_gem_bo_wait(drm_intel_bo *bo, uint64_t timeout_ns) This should bump the libdrm version. We're waiting for context support so we can do both features in one bump. v2: don't return remaining timeout amount use get param and fallback for older kernels v3: only doing getparam at init prototypes now have a signed input value v4: update comments fall back to correct polling behavior with new userspace and old kernel v5: since the drmIoctl patch was not well received, return appropriate values in this function instead. As Daniel pointed out, the polling case (timeout == 0) should also return -ETIME. Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Daniel Vetter <[email protected]> diff --git a/intel/intel_bufmgr.h b/intel/intel_bufmgr.h index c197abc..fa6c4dd 100644 --- a/intel/intel_bufmgr.h +++ b/intel/intel_bufmgr.h @@ -184,6 +184,7 @@ int drm_intel_get_pipe_from_crtc_id(drm_intel_bufmgr *bufmgr, int crtc_id); int drm_intel_get_aperture_sizes(int fd, size_t *mappable, size_t *total); int drm_intel_bufmgr_gem_get_devid(drm_intel_bufmgr *bufmgr); +int drm_intel_gem_bo_wait(drm_intel_bo *bo, int64_t timeout_ns); /* drm_intel_bufmgr_fake.c */ drm_intel_bufmgr *drm_intel_bufmgr_fake_init(int fd, diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c index b776d2f..e90f8bd 100644 --- a/intel/intel_bufmgr_gem.c +++ b/intel/intel_bufmgr_gem.c @@ -119,6 +119,7 @@ typedef struct _drm_intel_bufmgr_gem { unsigned int has_blt : 1; unsigned int has_relaxed_fencing : 1; unsigned int has_llc : 1; + unsigned int has_wait_timeout : 1; unsigned int bo_reuse : 1; unsigned int no_exec : 1; bool fenced_relocs; @@ -1479,6 +1480,58 @@ drm_intel_gem_bo_wait_rendering(drm_intel_bo *bo) } /** + * Waits on a BO for the given amount of time. + * + * @bo: buffer object to wait for + * @timeout_ns: amount of time to wait in nanoseconds. + * If value is less than 0, an infinite wait will occur. + * + * Returns 0 if the wait was successful ie. the last batch referencing the + * object has completed within the allotted time. Otherwise some negative return + * value describes the error. Of particular interest is -ETIME when the wait has + * failed to yield the desired result. + * + * Similar to drm_intel_gem_bo_wait_rendering except a timeout parameter allows + * the operation to give up after a certain amount of time. Another subtle + * difference is the internal locking semantics are different (this variant does + * not hold the lock for the duration of the wait). This makes the wait subject + * to a larger userspace race window. + * + * The implementation shall wait until the object is no longer actively + * referenced within a batch buffer at the time of the call. The wait will + * not guarantee that the buffer is re-issued via another thread, or an flinked + * handle. Userspace must make sure this race does not occur if such precision + * is important. + */ +int drm_intel_gem_bo_wait(drm_intel_bo *bo, int64_t timeout_ns) +{ + drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr; + drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; + struct drm_i915_gem_wait wait; + int ret; + + if (!bufmgr_gem->has_wait_timeout) { + DBG("%s:%d: Timed wait is not supported. Falling back to " + "infinite wait\n", __FILE__, __LINE__); + if (timeout_ns) { + drm_intel_gem_bo_wait_rendering(bo); + return 0; + } else { + return drm_intel_gem_bo_busy(bo) ? -ETIME : 0; + } + } + + wait.bo_handle = bo_gem->gem_handle; + wait.timeout_ns = timeout_ns; + wait.flags = 0; + ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_WAIT, &wait); + if (ret == -1) + return -errno; + + return ret; +} + +/** * Sets the object to the GTT read and possibly write domain, used by the X * 2D driver in the absence of kernel support to do drm_intel_gem_bo_map_gtt(). * @@ -2898,6 +2951,10 @@ drm_intel_bufmgr_gem_init(int fd, int batch_size) ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp); bufmgr_gem->has_relaxed_fencing = ret == 0; + gp.param = I915_PARAM_HAS_WAIT_TIMEOUT; + ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp); + bufmgr_gem->has_wait_timeout = ret == 0; + gp.param = I915_PARAM_HAS_LLC; ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp); if (ret != 0) { commit ae137f4669ccdbc615d18facebdb804a9af9846b Author: Ben Widawsky <[email protected]> Date: Sun Jun 24 17:12:24 2012 -0700 intel: Add IVB PUSH_CONSTANT decodes Signed-off-by: Ben Widawsky <[email protected]> diff --git a/intel/intel_decode.c b/intel/intel_decode.c index bf23706..c9bfee4 100644 --- a/intel/intel_decode.c +++ b/intel/intel_decode.c @@ -3208,6 +3208,9 @@ decode_3d_965(struct drm_intel_decode *ctx) { 0x790d, 0xffff, 4, 4, "3DSTATE_MULTISAMPLE", 7 }, { 0x7910, 0xffff, 2, 2, "3DSTATE_CLEAR_PARAMS" }, { 0x7912, 0x00ff, 2, 2, "3DSTATE_PUSH_CONSTANT_ALLOC_VS" }, + { 0x7913, 0x00ff, 2, 2, "3DSTATE_PUSH_CONSTANT_ALLOC_HS" }, + { 0x7914, 0x00ff, 2, 2, "3DSTATE_PUSH_CONSTANT_ALLOC_DS" }, + { 0x7915, 0x00ff, 2, 2, "3DSTATE_PUSH_CONSTANT_ALLOC_GS" }, { 0x7916, 0x00ff, 2, 2, "3DSTATE_PUSH_CONSTANT_ALLOC_PS" }, { 0x7917, 0x00ff, 2, 2+128*2, "3DSTATE_SO_DECL_LIST" }, { 0x7918, 0x00ff, 4, 4, "3DSTATE_SO_BUFFER" }, commit a1d462d2a6f720538eaf1199a94dd27cd04e8a54 Author: Dave Airlie <[email protected]> Date: Sun Jun 17 09:18:03 2012 +0100 radeon/surface: free version after using it. fixes leak in valgrind. Signed-off-by: Dave Airlie <[email protected]> diff --git a/radeon/radeon_surface.c b/radeon/radeon_surface.c index 0afd596..c80f7f4 100644 --- a/radeon/radeon_surface.c +++ b/radeon/radeon_surface.c @@ -191,6 +191,7 @@ static int r6_init_hw_info(struct radeon_surface_manager *surf_man) if (version && version->version_minor >= 14) { surf_man->hw_info.allow_2d = 1; } + drmFreeVersion(version); switch ((tiling_config & 0xe) >> 1) { case 0: @@ -470,6 +471,7 @@ static int eg_init_hw_info(struct radeon_surface_manager *surf_man) if (version && version->version_minor >= 16) { surf_man->hw_info.allow_2d = 1; } + drmFreeVersion(version); switch (tiling_config & 0xf) { case 0: commit d1fcfb17b9642ae351b03056a27b328f314ca80a Author: Jerome Glisse <[email protected]> Date: Tue Jun 12 18:09:55 2012 -0400 radeon: force 1D array mode for z/stencil surface On r6xx or evergreen z/stencil surface don't support linear or linear aligned surface, force 1D tiled mode for those. Signed-off-by: Jerome Glisse <[email protected]> diff --git a/radeon/radeon_surface.c b/radeon/radeon_surface.c index 64a8dd4..0afd596 100644 --- a/radeon/radeon_surface.c +++ b/radeon/radeon_surface.c @@ -384,6 +384,27 @@ static int r6_surface_init(struct radeon_surface_manager *surf_man, /* tiling mode */ mode = (surf->flags >> RADEON_SURF_MODE_SHIFT) & RADEON_SURF_MODE_MASK; + /* always enable z & stencil together */ + if (surf->flags & RADEON_SURF_ZBUFFER) { + surf->flags |= RADEON_SURF_SBUFFER; + } + if (surf->flags & RADEON_SURF_SBUFFER) { + surf->flags |= RADEON_SURF_ZBUFFER; + } + if (surf->flags & RADEON_SURF_ZBUFFER) { + /* zbuffer only support 1D or 2D tiled surface */ + switch (mode) { + case RADEON_SURF_MODE_1D: + case RADEON_SURF_MODE_2D: + break; + default: + mode = RADEON_SURF_MODE_1D; + surf->flags = RADEON_SURF_CLR(surf->flags, MODE); + surf->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE); + break; + } + } + /* force 1d on kernel that can't do 2d */ if (!surf_man->hw_info.allow_2d && mode > RADEON_SURF_MODE_1D) { mode = RADEON_SURF_MODE_1D; @@ -740,6 +761,22 @@ static int eg_surface_init(struct radeon_surface_manager *surf_man, if (surf->flags & RADEON_SURF_ZBUFFER) { surf->flags |= RADEON_SURF_SBUFFER; } + if (surf->flags & RADEON_SURF_SBUFFER) { + surf->flags |= RADEON_SURF_ZBUFFER; + } + if (surf->flags & RADEON_SURF_ZBUFFER) { + /* zbuffer only support 1D or 2D tiled surface */ + switch (mode) { + case RADEON_SURF_MODE_1D: + case RADEON_SURF_MODE_2D: + break; + default: + mode = RADEON_SURF_MODE_1D; + surf->flags = RADEON_SURF_CLR(surf->flags, MODE); + surf->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE); + break; + } + } r = eg_surface_sanity(surf_man, surf, mode); if (r) { commit 2f56002cc0b5424902dfe2bd4024f7b825ecde67 Author: Jerome Glisse <[email protected]> Date: Mon Jun 11 15:04:45 2012 -0400 radeon: enabled 2D tiling for evergreen only on fixed kernel Due to a kernel bug, enabled 2D tiling for evergreen only on newer fixed kernel. Signed-off-by: Jerome Glisse <[email protected]> diff --git a/radeon/radeon_surface.c b/radeon/radeon_surface.c index 704d8e7..64a8dd4 100644 --- a/radeon/radeon_surface.c +++ b/radeon/radeon_surface.c @@ -446,7 +446,7 @@ static int eg_init_hw_info(struct radeon_surface_manager *surf_man) surf_man->hw_info.allow_2d = 0; version = drmGetVersion(surf_man->fd); - if (version && version->version_minor >= 14) { + if (version && version->version_minor >= 16) { surf_man->hw_info.allow_2d = 1; } commit 325e2e52a96ede6a19e891f769c803cb9ba85e10 Author: Jerome Glisse <[email protected]> Date: Mon Jun 11 15:01:12 2012 -0400 radeon: always properly initialize stencil_offset field Reported-by: Vadim Girlin <[email protected]> Signed-off-by: Jerome Glisse <[email protected]> diff --git a/radeon/radeon_surface.c b/radeon/radeon_surface.c index adf209d..704d8e7 100644 --- a/radeon/radeon_surface.c +++ b/radeon/radeon_surface.c @@ -565,8 +565,6 @@ static int eg_surface_init_1d(struct radeon_surface_manager *surf_man, tilew = 8; xalign = surf_man->hw_info.group_bytes / (tilew * surf->bpe * surf->nsamples); if (surf->flags & RADEON_SURF_SBUFFER) { - surf->stencil_offset = 0; - surf->stencil_tile_split = 0; xalign = surf_man->hw_info.group_bytes / (tilew * surf->nsamples); } xalign = MAX2(tilew, xalign); @@ -607,7 +605,6 @@ static int eg_surface_init_2d(struct radeon_surface_manager *surf_man, unsigned slice_pt; unsigned i; - surf->stencil_offset = 0; /* compute tile values */ tilew = 8; tileh = 8; @@ -749,6 +746,9 @@ static int eg_surface_init(struct radeon_surface_manager *surf_man, return r; } + surf->stencil_offset = 0; + surf->stencil_tile_split = 0; + /* check tiling mode */ switch (mode) { case RADEON_SURF_MODE_LINEAR: commit 9e0026d35c56374b53a0b3837e24412bc9a4d8c9 Author: Marcin Slusarz <[email protected]> Date: Sat Jun 9 20:56:37 2012 +0200 nouveau: silence some remaining valgrind warnings Valgrind can't understand some of the fields passed to ioctls are overwritten by kernel, so we need to initialize them. Almost all of our ioctl wrappers already do it and the cost of remaining 3 is very small. Signed-off-by: Marcin Slusarz <[email protected]> diff --git a/nouveau/abi16.c b/nouveau/abi16.c index 69a0a9b..a67fbc1 100644 --- a/nouveau/abi16.c +++ b/nouveau/abi16.c @@ -31,13 +31,10 @@ int abi16_chan_nv04(struct nouveau_object *obj) { struct nouveau_device *dev = (struct nouveau_device *)obj->parent; - struct drm_nouveau_channel_alloc req; struct nv04_fifo *nv04 = obj->data; + struct drm_nouveau_channel_alloc req = {nv04->vram, nv04->gart}; int ret; - req.fb_ctxdma_handle = nv04->vram; - req.tt_ctxdma_handle = nv04->gart; - ret = drmCommandWriteRead(dev->fd, DRM_NOUVEAU_CHANNEL_ALLOC, &req, sizeof(req)); if (ret) diff --git a/nouveau/pushbuf.c b/nouveau/pushbuf.c index 7b9dbaa..0e37ce3 100644 -- To UNSUBSCRIBE, email to [email protected] with a subject of "unsubscribe". Trouble? Contact [email protected] Archive: http://lists.debian.org/[email protected]
