.gitignore | 4 ChangeLog | 254 ++++++++++++ Makefile.am | 2 configure.ac | 50 ++ debian/changelog | 3 debian/libdrm-dev.install | 1 debian/patches/02_build_libkms_against_in_tree_drm.diff | 17 debian/patches/series | 1 debian/rules | 4 intel/intel_bufmgr_gem.c | 10 intel/intel_chipset.h | 7 intel/intel_decode.c | 2 libkms/Makefile.am | 2 man/Makefile.am | 11 man/drmAvailable.man | 25 + man/drmHandleEvent.man | 45 ++ man/drmModeGetResources.man | 79 +++ omap/omap_drm.c | 2 radeon/r600_pci_ids.h | 3 radeon/radeon_cs_gem.c | 2 radeon/radeon_surface.c | 333 ++++++++++++---- radeon/radeon_surface.h | 2 tests/modetest/Makefile.am | 11 xf86drmMode.c | 5 24 files changed, 758 insertions(+), 117 deletions(-)
New commits: commit c8352e15c1f267e3d6e97cd1aaf2f9942c3f8224 Author: Sven Joachim <[email protected]> Date: Thu Nov 15 20:31:16 2012 +0100 Install section manpages into the libdrm-dev package Commit 2426a6a7112ae62755408a371831eddbe2d89d99 introduced these manpages. diff --git a/debian/libdrm-dev.install b/debian/libdrm-dev.install index 76f28fa..e1ca993 100644 --- a/debian/libdrm-dev.install +++ b/debian/libdrm-dev.install @@ -2,3 +2,4 @@ usr/include/* usr/lib/*/lib*.a usr/lib/*/lib*.so usr/lib/*/pkgconfig/* +usr/share/man/man3 commit fb429907b6d74074557b41d9fbe098b5f4235904 Author: Sven Joachim <[email protected]> Date: Thu Nov 15 20:31:00 2012 +0100 Fix vmwgfx confflags Since commit 7080bfdfd9b6c5f003daaef37ae9c329f2d46a6c vmwgfx is no longer considered experimental. diff --git a/debian/rules b/debian/rules index 616c968..5019c24 100755 --- a/debian/rules +++ b/debian/rules @@ -13,7 +13,7 @@ ifeq (linux, $(DEB_HOST_ARCH_OS)) confflags += --enable-udev confflags += --enable-libkms LIBKMS = yes - confflags += --enable-vmwgfx-experimental-api + confflags += --enable-vmwgfx confflags += --enable-nouveau NOUVEAU = yes confflags += --enable-radeon @@ -22,7 +22,7 @@ else confflags += --disable-udev confflags += --disable-libkms LIBKMS = no - confflags += --disable-vmwgfx-experimental-api + confflags += --disable-vmwgfx confflags += --disable-nouveau NOUVEAU = no confflags += --disable-radeon commit 1d729dd500fc700cf75c61e11fdaadbe8c76298b Author: Sven Joachim <[email protected]> Date: Thu Nov 15 20:30:43 2012 +0100 Drop patch 02_build_libkms_against_in_tree_drm.diff Applied upstream in commit 9c3c95fc0cb0945492279f0c7dcc0c2b1e8f463d. diff --git a/debian/changelog b/debian/changelog index 92f7b15..670b870 100644 --- a/debian/changelog +++ b/debian/changelog @@ -15,6 +15,7 @@ libdrm (2.4.40-1) UNRELEASED; urgency=low [ Sven Joachim ] * Bump libdrm-radeon1's symbols and shlibs. * Mark some internal libdrm-nouveau2 symbols as private. + * Drop patch 02_build_libkms_against_in_tree_drm.diff, applied upstream. -- Christopher James Halse Rogers <[email protected]> Tue, 21 Aug 2012 14:05:52 +1000 diff --git a/debian/patches/02_build_libkms_against_in_tree_drm.diff b/debian/patches/02_build_libkms_against_in_tree_drm.diff deleted file mode 100644 index 25f8e43..0000000 --- a/debian/patches/02_build_libkms_against_in_tree_drm.diff +++ /dev/null @@ -1,17 +0,0 @@ -Description: Add libdrm to LIBADD as libkms uses symbols from libdrm -Author: Christopher Halse Rogers <[email protected]> -Bug: https://bugs.freedesktop.org/show_bug.cgi?id=26852 - -Index: libdrm/libkms/Makefile.am -=================================================================== ---- libdrm.orig/libkms/Makefile.am -+++ libdrm/libkms/Makefile.am -@@ -6,7 +6,7 @@ AM_CFLAGS = \ - libkms_la_LTLIBRARIES = libkms.la - libkms_ladir = $(libdir) - libkms_la_LDFLAGS = -version-number 1:0:0 -no-undefined --libkms_la_LIBADD = -+libkms_la_LIBADD = ../libdrm.la - - #if HAVE_LIBUDEV - #libkms_la_LIBADD += $(LIBUDEV_LIBS) diff --git a/debian/patches/series b/debian/patches/series index b1a73f8..2e425c0 100644 --- a/debian/patches/series +++ b/debian/patches/series @@ -1,3 +1,2 @@ 01_default_perms.diff -02_build_libkms_against_in_tree_drm.diff 03_build_against_librt.diff commit f19d74deb831035d470d04b9d2802203895a97b8 Author: Sven Joachim <[email protected]> Date: Thu Nov 15 20:30:19 2012 +0100 New upstream release diff --git a/ChangeLog b/ChangeLog index 461676b..53b397c 100644 --- a/ChangeLog +++ b/ChangeLog @@ -1,3 +1,257 @@ +commit e01d68f9f3acfc35fe164283904b5d058c2ab378 +Author: Marek Olšák <[email protected]> +Date: Tue Nov 6 01:23:53 2012 +0100 + + configure.ac: bump version to 2.4.40 for release + +commit 2089a0080edb1b42449ee9a97f2cef7399c16d53 +Author: Dave Airlie <[email protected]> +Date: Mon Nov 5 22:21:42 2012 +0000 + + fix make distcheck + + typo, + + Reported-by: mareko on irc + Signed-off-by: Dave Airlie <[email protected]> + +commit e32fff8e9ea8d522679eaab21a9555cab134fb36 +Author: Marek Olšák <[email protected]> +Date: Tue Oct 16 02:08:02 2012 +0200 + + radeon: fix tile_split of 128-bit surface formats with 8x MSAA + + The calculation led to the number 8192, which is too high. + + Reviewed-by: Alex Deucher <[email protected]> + +commit bc494b310d76f701798aee0f2b0b472d608cbfaf +Author: Andreas Boll <[email protected]> +Date: Tue Aug 28 12:49:45 2012 +0200 + + radeon: fix unused-function warning + + radeon_cs_gem.c:333:13: warning: 'cs_gem_dump_bof' defined but + not used [-Wunused-function] + + Reviewed-by: Alex Deucher <[email protected]> + +commit a4cb7233a8da171e53b48b376be5c1265c29a612 +Author: Alex Deucher <[email protected]> +Date: Tue Oct 16 12:58:39 2012 -0400 + + radeon: add some new SI pci ids + + Signed-off-by: Alex Deucher <[email protected]> + +commit e81acf51013d5d4245417c46ee6b4055c26f1a91 +Author: Rob Clark <[email protected]> +Date: Sun Oct 14 16:55:32 2012 -0500 + + initialize width/height fields in drmModeCrtc + + If we have valid timings, we can at least set width/height to + *something*, which is I think at least less confusing than always + seeing width/height of zero. At least modeprint and modetest + seem to expect width/height to mean something. + + Signed-off-by: Rob Clark <[email protected]> + +commit 844d75e5a0b3b8f3466a24256955e886275fb298 +Author: Rob Clark <[email protected]> +Date: Tue Oct 9 09:48:56 2012 -0500 + + update gitignore + + Signed-off-by: Rob Clark <[email protected]> + +commit 28a13f0be734958c74ae5a23d9cf766fa0857a62 +Author: Vincent Penquerc'h <[email protected]> +Date: Tue Oct 9 14:48:34 2012 +0100 + + omap: release lock also on error paths + + Signed-off-by: Rob Clark <[email protected]> + +commit 14db948127e549ea9234e02d8e112de3871f8f9f +Author: Daniel Stone <[email protected]> +Date: Thu Oct 4 01:21:57 2012 +0000 + + configure.ac: Allow forcible disabling of Cairo support + + We don't want to build libdrm tests with Cairo support under Poky, since + they're never used and also cause a build loop from libdrm -> cairo -> + mesa-dri -> libdrm. + + To avoid variance in build results, introduce a --disable-cairo-tests + switch. + + Signed-off-by: Daniel Stone <[email protected]> + Signed-off-by: Dave Airlie <[email protected]> + +commit a83444c925b18b3db431336360d6915aaf21f727 +Author: Chris Wilson <[email protected]> +Date: Sun Oct 7 10:08:46 2012 +0100 + + intel: Silence a trivial compiler warning + + intel_bufmgr_gem.c: In function 'drm_intel_bo_gem_export_to_prime': + intel_bufmgr_gem.c:2477:6: warning: unused variable 'ret' [-Wunused-variable] + + Signed-off-by: Chris Wilson <[email protected]> + +commit 8cf3475eb5d887c361db372a644d0d1a11e137f8 +Author: Chris Wilson <[email protected]> +Date: Sun Oct 7 10:07:23 2012 +0100 + + intel: Correct the word decoding for gen2 3DSTATE_LOAD_STATE_IMMEDIATE_1 + + Signed-off-by: Chris Wilson <[email protected]> + +commit 75830a0d2cbb614ecc3f7e6b516ec595bb41d6a3 +Author: Chris Wilson <[email protected]> +Date: Sun Oct 7 10:05:19 2012 +0100 + + intel: Fix "properly test for HAS_LLC" + + commit 92fd0ce4f659d7b0680543e9e5b96a3c7737a5f3 + Author: Daniel Vetter <[email protected]> + Date: Fri Aug 31 11:16:53 2012 +0200 + + intel: properly test for HAS_LLC + + missed slightly and in effect had no effect on the outcome of checking + whether the kernel/chipset supported LLC. + + Signed-off-by: Chris Wilson <[email protected]> + +commit 1aebfdc1121ccb6babb3a63dc0b99d68b4860b04 +Author: Marek Olšák <[email protected]> +Date: Sun Sep 30 19:20:04 2012 +0200 + + radeon: fix stencil miptree allocation of combined ZS buffers on EG and SI + + This allows texturing with depth-stencil buffers directly without the copy + to CB. The separate miptree description for stencil is added, because + the stencil mipmap offsets are not really depth offsets/4 (at least + for the texture units). + + Reviewed-by: Alex Deucher <[email protected]> + +commit 77413e77b82a5d800c86b7d3b864d6cc797721c9 +Author: Marek Olšák <[email protected]> +Date: Sun Sep 30 19:19:13 2012 +0200 + + radeon: don't force stencil tile split to 0 + + Reviewed-by: Alex Deucher <[email protected]> + +commit b3d90bbc1d43bb11d8de25109f403b1b30533c34 +Author: Marek Olšák <[email protected]> +Date: Sat Sep 29 15:10:33 2012 +0200 + + radeon: don't take the stencil-specific codepath for buffers without stencil + + Reviewed-by: Alex Deucher <[email protected]> + +commit 2426a6a7112ae62755408a371831eddbe2d89d99 +Author: Jesse Barnes <[email protected]> +Date: Thu Sep 6 16:16:50 2012 -0700 + + libdrm: man page infrastructure and a few sample man pages + +commit 1b7ce582ceac74c7c5f1989c611b4f01a2a18434 +Author: Kristian Høgsberg <[email protected]> +Date: Fri Sep 14 16:35:19 2012 -0400 + + intel: Mark bo's exported to prime as not reusable + + It's the same situation as flink and we need take the same precautions. + + Reviewed-by: Chris Wilson <[email protected]> + Signed-off-by: Kristian Høgsberg <[email protected]> + +commit 9d9cb8553c945fac15421770da233fb3e38396e0 +Author: Jesse Barnes <[email protected]> +Date: Sun Mar 18 16:51:18 2012 -0500 + + intel: add support for ValleyView + + Just some PCI ID stuff to enable the right features. + +commit 9c3c95fc0cb0945492279f0c7dcc0c2b1e8f463d +Author: Marcin Slusarz <[email protected]> +Date: Sat Sep 8 00:49:38 2012 +0200 + + libkms: link against libdrm + + Signed-off-by: Marcin Slusarz <[email protected]> + +commit b925022a3e4616665b388a78abab4e3270b4b4ec +Author: Michel Dänzer <[email protected]> +Date: Wed Sep 5 18:44:45 2012 +0200 + + radeon: Sampling pitch for non-mipmaps seems padded to slice alignment on SI. + + Another corner case that isn't well-explained yet. + + Signed-off-by: Michel Dänzer <[email protected]> + Reviewed-by: Christian König <[email protected]> + +commit 45083e6d36125c64267c917da3d81e1e144ed33d +Author: Michel Dänzer <[email protected]> +Date: Tue Sep 4 18:53:55 2012 +0200 + + radeon: Memory footprint of SI mipmap base level is padded to powers of two. + + Signed-off-by: Michel Dänzer <[email protected]> + Reviewed-by: Christian König <[email protected]> + +commit 8572444fd0cda3e7b9557c09d2d0f7a9e049a2e7 +Author: Michel Dänzer <[email protected]> +Date: Fri Aug 31 19:29:33 2012 +0200 + + radeon: Fix layout of linear aligned mipmaps on SI. + + Signed-off-by: Michel Dänzer <[email protected]> + Reviewed-by: Christian König <[email protected]> + +commit 92fd0ce4f659d7b0680543e9e5b96a3c7737a5f3 +Author: Daniel Vetter <[email protected]> +Date: Fri Aug 31 11:16:53 2012 +0200 + + intel: properly test for HAS_LLC + + If the kernel supports the test, we need to check the param. + Copy&pasta from the above checks that only look at the return value. + Interesting how much one can get such a simple interface wrong. + + Issue created in + + commit 151cdcfe685ee280a4344dfc40e6087d74a5590f + Author: Eugeni Dodonov <[email protected]> + Date: Tue Jan 17 15:20:19 2012 -0200 + + intel: query for LLC support + + Patch even claims to have fixed this in v2, but is actually unchanged + from v1. + + Reported-by: Xiang, Haihao <[email protected]> + Reviewed-by: Chris Wilson <[email protected]> + Signed-off-by: Daniel Vetter <[email protected]> + +commit 7080bfdfd9b6c5f003daaef37ae9c329f2d46a6c +Author: Jakob Bornecrantz <[email protected]> +Date: Mon Aug 13 13:35:07 2012 +0200 + + vmwgfx: No longer experimental + + And hasn't been in a long while. + + Reviewed-by: Zack Rusin <[email protected]> + Signed-off-by: Jakob Bornecrantz <[email protected]> + commit ae3ac8225fe1c6781ce425c57ef5fb6c5af6ccf4 Author: Marek Olšák <[email protected]> Date: Fri Aug 24 17:03:13 2012 +0200 diff --git a/debian/changelog b/debian/changelog index 51d7487..92f7b15 100644 --- a/debian/changelog +++ b/debian/changelog @@ -1,4 +1,4 @@ -libdrm (2.4.39-1) UNRELEASED; urgency=low +libdrm (2.4.40-1) UNRELEASED; urgency=low [ Maarten Lankhorst ] * New upstream release. commit e01d68f9f3acfc35fe164283904b5d058c2ab378 Author: Marek Olšák <[email protected]> Date: Tue Nov 6 01:23:53 2012 +0100 configure.ac: bump version to 2.4.40 for release diff --git a/configure.ac b/configure.ac index 8c28107..0c19929 100644 --- a/configure.ac +++ b/configure.ac @@ -20,7 +20,7 @@ AC_PREREQ([2.63]) AC_INIT([libdrm], - [2.4.39], + [2.4.40], [https://bugs.freedesktop.org/enter_bug.cgi?product=DRI], [libdrm]) commit 2089a0080edb1b42449ee9a97f2cef7399c16d53 Author: Dave Airlie <[email protected]> Date: Mon Nov 5 22:21:42 2012 +0000 fix make distcheck typo, Reported-by: mareko on irc Signed-off-by: Dave Airlie <[email protected]> diff --git a/man/Makefile.am b/man/Makefile.am index 73068e6..ccd6545 100644 --- a/man/Makefile.am +++ b/man/Makefile.am @@ -4,7 +4,7 @@ libman_PRE = drmAvailable.man \ drmModeGetResources.man libman_DATA = $(libman_PRE:man=@LIB_MAN_SUFFIX@) EXTRA_DIST = $(libman_PRE) -CLEANFILE = $(libman_DATA) +CLEANFILES = $(libman_DATA) SUFFIXES = .$(LIB_MAN_SUFFIX) .man .man.$(LIB_MAN_SUFFIX): commit e32fff8e9ea8d522679eaab21a9555cab134fb36 Author: Marek Olšák <[email protected]> Date: Tue Oct 16 02:08:02 2012 +0200 radeon: fix tile_split of 128-bit surface formats with 8x MSAA The calculation led to the number 8192, which is too high. Reviewed-by: Alex Deucher <[email protected]> diff --git a/radeon/radeon_surface.c b/radeon/radeon_surface.c index 66c2444..eb587d2 100644 --- a/radeon/radeon_surface.c +++ b/radeon/radeon_surface.c @@ -939,6 +939,8 @@ static int eg_surface_best(struct radeon_surface_manager *surf_man, } else { /* tile split must be >= 256 for colorbuffer surfaces */ surf->tile_split = MAX2(surf->nsamples * surf->bpe * 64, 256); + if (surf->tile_split > 4096) + surf->tile_split = 4096; } } else { /* set tile split to row size */ commit bc494b310d76f701798aee0f2b0b472d608cbfaf Author: Andreas Boll <[email protected]> Date: Tue Aug 28 12:49:45 2012 +0200 radeon: fix unused-function warning radeon_cs_gem.c:333:13: warning: 'cs_gem_dump_bof' defined but not used [-Wunused-function] Reviewed-by: Alex Deucher <[email protected]> diff --git a/radeon/radeon_cs_gem.c b/radeon/radeon_cs_gem.c index 9834bcf..b963140 100644 --- a/radeon/radeon_cs_gem.c +++ b/radeon/radeon_cs_gem.c @@ -330,6 +330,7 @@ static int cs_gem_end(struct radeon_cs_int *cs, return 0; } +#if CS_BOF_DUMP static void cs_gem_dump_bof(struct radeon_cs_int *cs) { struct cs_gem *csg = (struct cs_gem*)cs; @@ -415,6 +416,7 @@ out_err: bof_decref(device_id); bof_decref(root); } +#endif static int cs_gem_emit(struct radeon_cs_int *cs) { commit a4cb7233a8da171e53b48b376be5c1265c29a612 Author: Alex Deucher <[email protected]> Date: Tue Oct 16 12:58:39 2012 -0400 radeon: add some new SI pci ids Signed-off-by: Alex Deucher <[email protected]> diff --git a/radeon/r600_pci_ids.h b/radeon/r600_pci_ids.h index 12daafd..b9a85db 100644 --- a/radeon/r600_pci_ids.h +++ b/radeon/r600_pci_ids.h @@ -318,6 +318,8 @@ CHIPSET(0x6784, TAHITI_6784, TAHITI) CHIPSET(0x6788, TAHITI_6788, TAHITI) CHIPSET(0x678A, TAHITI_678A, TAHITI) CHIPSET(0x6790, TAHITI_6790, TAHITI) +CHIPSET(0x6791, TAHITI_6791, TAHITI) +CHIPSET(0x6792, TAHITI_6792, TAHITI) CHIPSET(0x6798, TAHITI_6798, TAHITI) CHIPSET(0x6799, TAHITI_6799, TAHITI) CHIPSET(0x679A, TAHITI_679A, TAHITI) @@ -331,6 +333,7 @@ CHIPSET(0x6806, PITCAIRN_6806, PITCAIRN) CHIPSET(0x6808, PITCAIRN_6808, PITCAIRN) CHIPSET(0x6809, PITCAIRN_6809, PITCAIRN) CHIPSET(0x6810, PITCAIRN_6810, PITCAIRN) +CHIPSET(0x6811, PITCAIRN_6811, PITCAIRN) CHIPSET(0x6816, PITCAIRN_6816, PITCAIRN) CHIPSET(0x6817, PITCAIRN_6817, PITCAIRN) CHIPSET(0x6818, PITCAIRN_6818, PITCAIRN) commit e81acf51013d5d4245417c46ee6b4055c26f1a91 Author: Rob Clark <[email protected]> Date: Sun Oct 14 16:55:32 2012 -0500 initialize width/height fields in drmModeCrtc If we have valid timings, we can at least set width/height to *something*, which is I think at least less confusing than always seeing width/height of zero. At least modeprint and modetest seem to expect width/height to mean something. Signed-off-by: Rob Clark <[email protected]> diff --git a/xf86drmMode.c b/xf86drmMode.c index 04fdf1f..f603ceb 100644 --- a/xf86drmMode.c +++ b/xf86drmMode.c @@ -351,8 +351,11 @@ drmModeCrtcPtr drmModeGetCrtc(int fd, uint32_t crtcId) r->x = crtc.x; r->y = crtc.y; r->mode_valid = crtc.mode_valid; - if (r->mode_valid) + if (r->mode_valid) { memcpy(&r->mode, &crtc.mode, sizeof(struct drm_mode_modeinfo)); + r->width = crtc.mode.hdisplay; + r->height = crtc.mode.vdisplay; + } r->buffer_id = crtc.fb_id; r->gamma_size = crtc.gamma_size; return r; commit 844d75e5a0b3b8f3466a24256955e886275fb298 Author: Rob Clark <[email protected]> Date: Tue Oct 9 09:48:56 2012 -0500 update gitignore Signed-off-by: Rob Clark <[email protected]> diff --git a/.gitignore b/.gitignore index 243457e..28c77c5 100644 --- a/.gitignore +++ b/.gitignore @@ -42,6 +42,8 @@ libdrm.pc libdrm_intel.pc libdrm_nouveau.pc libdrm_radeon.pc +libdrm_omap.pc +libdrm_exynos.pc libkms.pc libtool ltmain.sh @@ -76,3 +78,5 @@ tests/modeprint/modeprint tests/modetest/modetest tests/kmstest/kmstest tests/vbltest/vbltest +tests/radeon/radeon_ttm +man/*.3 commit 28a13f0be734958c74ae5a23d9cf766fa0857a62 Author: Vincent Penquerc'h <[email protected]> Date: Tue Oct 9 14:48:34 2012 +0100 omap: release lock also on error paths Signed-off-by: Rob Clark <[email protected]> diff --git a/omap/omap_drm.c b/omap/omap_drm.c index cd8e8bc..89f1491 100644 --- a/omap/omap_drm.c +++ b/omap/omap_drm.c @@ -304,6 +304,7 @@ struct omap_bo * omap_bo_from_name(struct omap_device *dev, uint32_t name) return bo; fail: + pthread_mutex_unlock(&table_lock); free(bo); return NULL; } @@ -337,6 +338,7 @@ struct omap_bo * omap_bo_from_dmabuf(struct omap_device *dev, int fd) return bo; fail: + pthread_mutex_unlock(&table_lock); free(bo); return NULL; } commit 14db948127e549ea9234e02d8e112de3871f8f9f Author: Daniel Stone <[email protected]> Date: Thu Oct 4 01:21:57 2012 +0000 configure.ac: Allow forcible disabling of Cairo support We don't want to build libdrm tests with Cairo support under Poky, since they're never used and also cause a build loop from libdrm -> cairo -> mesa-dri -> libdrm. To avoid variance in build results, introduce a --disable-cairo-tests switch. Signed-off-by: Daniel Stone <[email protected]> Signed-off-by: Dave Airlie <[email protected]> diff --git a/configure.ac b/configure.ac index 290362c..8c28107 100644 --- a/configure.ac +++ b/configure.ac @@ -222,11 +222,23 @@ if test "x$EXYNOS" = xyes; then AC_DEFINE(HAVE_EXYNOS, 1, [Have EXYNOS support]) fi +AC_ARG_ENABLE([cairo-tests], + [AS_HELP_STRING([--enable-cairo-tests], + [Enable support for Cairo rendering in tests (default: auto)])], + [CAIRO=$enableval], [CAIRO=auto]) PKG_CHECK_MODULES(CAIRO, cairo, [HAVE_CAIRO=yes], [HAVE_CAIRO=no]) -if test "x$HAVE_CAIRO" = xyes; then - AC_DEFINE(HAVE_CAIRO, 1, [Have cairo support]) +AC_MSG_CHECKING([whether to enable Cairo tests]) +if test "x$CAIRO" = xauto; then + CAIRO="$HAVE_CAIRO" fi -AM_CONDITIONAL(HAVE_CAIRO, [test "x$HAVE_CAIRO" = xyes]) +if test "x$CAIRO" = xyes; then + if ! test "x$HAVE_CAIRO" = xyes; then + AC_MSG_ERROR([Cairo support required but not present]) + fi + AC_DEFINE(HAVE_CAIRO, 1, [Have Cairo support]) +fi +AC_MSG_RESULT([$CAIRO]) +AM_CONDITIONAL(HAVE_CAIRO, [test "x$CAIRO" = xyes]) # For enumerating devices in test case PKG_CHECK_MODULES(LIBUDEV, libudev, [HAVE_LIBUDEV=yes], [HAVE_LIBUDEV=no]) diff --git a/tests/modetest/Makefile.am b/tests/modetest/Makefile.am index b5ec771..065ae13 100644 --- a/tests/modetest/Makefile.am +++ b/tests/modetest/Makefile.am @@ -1,8 +1,7 @@ AM_CFLAGS = \ -I$(top_srcdir)/include/drm \ -I$(top_srcdir)/libkms/ \ - -I$(top_srcdir) \ - $(CAIRO_CFLAGS) + -I$(top_srcdir) noinst_PROGRAMS = \ modetest @@ -12,5 +11,9 @@ modetest_SOURCES = \ modetest_LDADD = \ $(top_builddir)/libdrm.la \ - $(top_builddir)/libkms/libkms.la \ - $(CAIRO_LIBS) + $(top_builddir)/libkms/libkms.la + +if HAVE_CAIRO +AM_CFLAGS += $(CAIRO_CFLAGS) +modetest_LDADD += $(CAIRO_LIBS) +endif commit a83444c925b18b3db431336360d6915aaf21f727 Author: Chris Wilson <[email protected]> Date: Sun Oct 7 10:08:46 2012 +0100 intel: Silence a trivial compiler warning intel_bufmgr_gem.c: In function 'drm_intel_bo_gem_export_to_prime': intel_bufmgr_gem.c:2477:6: warning: unused variable 'ret' [-Wunused-variable] Signed-off-by: Chris Wilson <[email protected]> diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c index 3f7424c..8d45839 100644 --- a/intel/intel_bufmgr_gem.c +++ b/intel/intel_bufmgr_gem.c @@ -2472,7 +2472,6 @@ drm_intel_bo_gem_export_to_prime(drm_intel_bo *bo, int *prime_fd) { drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr; drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; - int ret; if (drmPrimeHandleToFD(bufmgr_gem->fd, bo_gem->gem_handle, DRM_CLOEXEC, prime_fd) != 0) commit 8cf3475eb5d887c361db372a644d0d1a11e137f8 Author: Chris Wilson <[email protected]> Date: Sun Oct 7 10:07:23 2012 +0100 intel: Correct the word decoding for gen2 3DSTATE_LOAD_STATE_IMMEDIATE_1 Signed-off-by: Chris Wilson <[email protected]> diff --git a/intel/intel_decode.c b/intel/intel_decode.c index 19a8d36..a4b045a 100644 --- a/intel/intel_decode.c +++ b/intel/intel_decode.c @@ -1714,7 +1714,7 @@ decode_3d_1d(struct drm_intel_decode *ctx) } } else { instr_out(ctx, i, - "S%d: 0x%08x\n", i, data[i]); + "S%d: 0x%08x\n", word, data[i]); } i++; } commit 75830a0d2cbb614ecc3f7e6b516ec595bb41d6a3 Author: Chris Wilson <[email protected]> Date: Sun Oct 7 10:05:19 2012 +0100 intel: Fix "properly test for HAS_LLC" commit 92fd0ce4f659d7b0680543e9e5b96a3c7737a5f3 Author: Daniel Vetter <[email protected]> Date: Fri Aug 31 11:16:53 2012 +0200 intel: properly test for HAS_LLC missed slightly and in effect had no effect on the outcome of checking whether the kernel/chipset supported LLC. Signed-off-by: Chris Wilson <[email protected]> diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c index 898008d..3f7424c 100644 --- a/intel/intel_bufmgr_gem.c +++ b/intel/intel_bufmgr_gem.c @@ -3119,7 +3119,7 @@ drm_intel_bufmgr_gem_init(int fd, int batch_size) bufmgr_gem->has_llc = (IS_GEN6(bufmgr_gem->pci_device) | IS_GEN7(bufmgr_gem->pci_device)); } else - bufmgr_gem->has_llc = gp.value; + bufmgr_gem->has_llc = *gp.value; if (bufmgr_gem->gen < 4) { gp.param = I915_PARAM_NUM_FENCES_AVAIL; commit 1aebfdc1121ccb6babb3a63dc0b99d68b4860b04 Author: Marek Olšák <[email protected]> Date: Sun Sep 30 19:20:04 2012 +0200 radeon: fix stencil miptree allocation of combined ZS buffers on EG and SI This allows texturing with depth-stencil buffers directly without the copy to CB. The separate miptree description for stencil is added, because the stencil mipmap offsets are not really depth offsets/4 (at least for the texture units). Reviewed-by: Alex Deucher <[email protected]> diff --git a/radeon/radeon_surface.c b/radeon/radeon_surface.c index c62cbf9..66c2444 100644 --- a/radeon/radeon_surface.c +++ b/radeon/radeon_surface.c @@ -144,31 +144,32 @@ static unsigned mip_minify(unsigned size, unsigned level) } static void surf_minify(struct radeon_surface *surf, - unsigned level, + struct radeon_surface_level *surflevel, + unsigned bpe, unsigned level, uint32_t xalign, uint32_t yalign, uint32_t zalign, unsigned offset) { - surf->level[level].npix_x = mip_minify(surf->npix_x, level); - surf->level[level].npix_y = mip_minify(surf->npix_y, level); - surf->level[level].npix_z = mip_minify(surf->npix_z, level); - surf->level[level].nblk_x = (surf->level[level].npix_x + surf->blk_w - 1) / surf->blk_w; - surf->level[level].nblk_y = (surf->level[level].npix_y + surf->blk_h - 1) / surf->blk_h; - surf->level[level].nblk_z = (surf->level[level].npix_z + surf->blk_d - 1) / surf->blk_d; - if (surf->nsamples == 1 && surf->level[level].mode == RADEON_SURF_MODE_2D) { - if (surf->level[level].nblk_x < xalign || surf->level[level].nblk_y < yalign) { - surf->level[level].mode = RADEON_SURF_MODE_1D; + surflevel->npix_x = mip_minify(surf->npix_x, level); + surflevel->npix_y = mip_minify(surf->npix_y, level); + surflevel->npix_z = mip_minify(surf->npix_z, level); + surflevel->nblk_x = (surflevel->npix_x + surf->blk_w - 1) / surf->blk_w; + surflevel->nblk_y = (surflevel->npix_y + surf->blk_h - 1) / surf->blk_h; + surflevel->nblk_z = (surflevel->npix_z + surf->blk_d - 1) / surf->blk_d; + if (surf->nsamples == 1 && surflevel->mode == RADEON_SURF_MODE_2D) { + if (surflevel->nblk_x < xalign || surflevel->nblk_y < yalign) { + surflevel->mode = RADEON_SURF_MODE_1D; return; } } - surf->level[level].nblk_x = ALIGN(surf->level[level].nblk_x, xalign); - surf->level[level].nblk_y = ALIGN(surf->level[level].nblk_y, yalign); - surf->level[level].nblk_z = ALIGN(surf->level[level].nblk_z, zalign); + surflevel->nblk_x = ALIGN(surflevel->nblk_x, xalign); + surflevel->nblk_y = ALIGN(surflevel->nblk_y, yalign); + surflevel->nblk_z = ALIGN(surflevel->nblk_z, zalign); - surf->level[level].offset = offset; - surf->level[level].pitch_bytes = surf->level[level].nblk_x * surf->bpe * surf->nsamples; - surf->level[level].slice_size = surf->level[level].pitch_bytes * surf->level[level].nblk_y; + surflevel->offset = offset; + surflevel->pitch_bytes = surflevel->nblk_x * bpe * surf->nsamples; + surflevel->slice_size = surflevel->pitch_bytes * surflevel->nblk_y; - surf->bo_size = offset + surf->level[level].slice_size * surf->level[level].nblk_z * surf->array_size; + surf->bo_size = offset + surflevel->slice_size * surflevel->nblk_z * surf->array_size; } /* =========================================================================== @@ -264,7 +265,7 @@ static int r6_surface_init_linear(struct radeon_surface_manager *surf_man, /* build mipmap tree */ for (i = start_level; i <= surf->last_level; i++) { surf->level[i].mode = RADEON_SURF_MODE_LINEAR; - surf_minify(surf, i, xalign, yalign, zalign, offset); + surf_minify(surf, surf->level+i, surf->bpe, i, xalign, yalign, zalign, offset); /* level0 and first mipmap need to have alignment */ offset = surf->bo_size; if ((i == 0)) { @@ -292,7 +293,7 @@ static int r6_surface_init_linear_aligned(struct radeon_surface_manager *surf_ma /* build mipmap tree */ for (i = start_level; i <= surf->last_level; i++) { surf->level[i].mode = RADEON_SURF_MODE_LINEAR_ALIGNED; - surf_minify(surf, i, xalign, yalign, zalign, offset); + surf_minify(surf, surf->level+i, surf->bpe, i, xalign, yalign, zalign, offset); /* level0 and first mipmap need to have alignment */ offset = surf->bo_size; if ((i == 0)) { @@ -325,7 +326,7 @@ static int r6_surface_init_1d(struct radeon_surface_manager *surf_man, /* build mipmap tree */ for (i = start_level; i <= surf->last_level; i++) { surf->level[i].mode = RADEON_SURF_MODE_1D; - surf_minify(surf, i, xalign, yalign, zalign, offset); + surf_minify(surf, surf->level+i, surf->bpe, i, xalign, yalign, zalign, offset); /* level0 and first mipmap need to have alignment */ offset = surf->bo_size; if ((i == 0)) { @@ -363,7 +364,7 @@ static int r6_surface_init_2d(struct radeon_surface_manager *surf_man, /* build mipmap tree */ for (i = start_level; i <= surf->last_level; i++) { surf->level[i].mode = RADEON_SURF_MODE_2D; - surf_minify(surf, i, xalign, yalign, zalign, offset); + surf_minify(surf, surf->level+i, surf->bpe, i, xalign, yalign, zalign, offset); if (surf->level[i].mode == RADEON_SURF_MODE_1D) { return r6_surface_init_1d(surf_man, surf, offset, i); } @@ -543,6 +544,8 @@ static int eg_init_hw_info(struct radeon_surface_manager *surf_man) } static void eg_surf_minify(struct radeon_surface *surf, + struct radeon_surface_level *surflevel, + unsigned bpe, unsigned level, unsigned slice_pt, unsigned mtilew, @@ -552,36 +555,38 @@ static void eg_surf_minify(struct radeon_surface *surf, { unsigned mtile_pr, mtile_ps; - surf->level[level].npix_x = mip_minify(surf->npix_x, level); - surf->level[level].npix_y = mip_minify(surf->npix_y, level); - surf->level[level].npix_z = mip_minify(surf->npix_z, level); - surf->level[level].nblk_x = (surf->level[level].npix_x + surf->blk_w - 1) / surf->blk_w; - surf->level[level].nblk_y = (surf->level[level].npix_y + surf->blk_h - 1) / surf->blk_h; - surf->level[level].nblk_z = (surf->level[level].npix_z + surf->blk_d - 1) / surf->blk_d; - if (surf->nsamples == 1 && surf->level[level].mode == RADEON_SURF_MODE_2D) { - if (surf->level[level].nblk_x < mtilew || surf->level[level].nblk_y < mtileh) { - surf->level[level].mode = RADEON_SURF_MODE_1D; + surflevel->npix_x = mip_minify(surf->npix_x, level); + surflevel->npix_y = mip_minify(surf->npix_y, level); + surflevel->npix_z = mip_minify(surf->npix_z, level); + surflevel->nblk_x = (surflevel->npix_x + surf->blk_w - 1) / surf->blk_w; + surflevel->nblk_y = (surflevel->npix_y + surf->blk_h - 1) / surf->blk_h; + surflevel->nblk_z = (surflevel->npix_z + surf->blk_d - 1) / surf->blk_d; + if (surf->nsamples == 1 && surflevel->mode == RADEON_SURF_MODE_2D) { + if (surflevel->nblk_x < mtilew || surflevel->nblk_y < mtileh) { + surflevel->mode = RADEON_SURF_MODE_1D; return; } } - surf->level[level].nblk_x = ALIGN(surf->level[level].nblk_x, mtilew); - surf->level[level].nblk_y = ALIGN(surf->level[level].nblk_y, mtileh); - surf->level[level].nblk_z = ALIGN(surf->level[level].nblk_z, 1); + surflevel->nblk_x = ALIGN(surflevel->nblk_x, mtilew); + surflevel->nblk_y = ALIGN(surflevel->nblk_y, mtileh); + surflevel->nblk_z = ALIGN(surflevel->nblk_z, 1); /* macro tile per row */ - mtile_pr = surf->level[level].nblk_x / mtilew; + mtile_pr = surflevel->nblk_x / mtilew; /* macro tile per slice */ - mtile_ps = (mtile_pr * surf->level[level].nblk_y) / mtileh; + mtile_ps = (mtile_pr * surflevel->nblk_y) / mtileh; - surf->level[level].offset = offset; - surf->level[level].pitch_bytes = surf->level[level].nblk_x * surf->bpe * slice_pt; - surf->level[level].slice_size = mtile_ps * mtileb * slice_pt; + surflevel->offset = offset; + surflevel->pitch_bytes = surflevel->nblk_x * bpe * slice_pt; + surflevel->slice_size = mtile_ps * mtileb * slice_pt; - surf->bo_size = offset + surf->level[level].slice_size * surf->level[level].nblk_z * surf->array_size; + surf->bo_size = offset + surflevel->slice_size * surflevel->nblk_z * surf->array_size; } static int eg_surface_init_1d(struct radeon_surface_manager *surf_man, struct radeon_surface *surf, + struct radeon_surface_level *level, + unsigned bpe, uint64_t offset, unsigned start_level) { uint32_t xalign, yalign, zalign, tilew; @@ -589,45 +594,40 @@ static int eg_surface_init_1d(struct radeon_surface_manager *surf_man, /* compute alignment */ tilew = 8; - xalign = surf_man->hw_info.group_bytes / (tilew * surf->bpe * surf->nsamples); - if (surf->flags & RADEON_SURF_SBUFFER) { - xalign = surf_man->hw_info.group_bytes / (tilew * surf->nsamples); - } + xalign = surf_man->hw_info.group_bytes / (tilew * bpe * surf->nsamples); xalign = MAX2(tilew, xalign); yalign = tilew; zalign = 1; if (surf->flags & RADEON_SURF_SCANOUT) { - xalign = MAX2((surf->bpe == 1) ? 64 : 32, xalign); + xalign = MAX2((bpe == 1) ? 64 : 32, xalign); } + if (!start_level) { - surf->bo_alignment = MAX2(256, surf_man->hw_info.group_bytes); + unsigned alignment = MAX2(256, surf_man->hw_info.group_bytes); + surf->bo_alignment = MAX2(surf->bo_alignment, alignment); + + if (offset) { + offset = ALIGN(offset, alignment); + } } /* build mipmap tree */ for (i = start_level; i <= surf->last_level; i++) { - surf->level[i].mode = RADEON_SURF_MODE_1D; - surf_minify(surf, i, xalign, yalign, zalign, offset); + level[i].mode = RADEON_SURF_MODE_1D; + surf_minify(surf, level+i, bpe, i, xalign, yalign, zalign, offset); /* level0 and first mipmap need to have alignment */ offset = surf->bo_size; if ((i == 0)) { offset = ALIGN(offset, surf->bo_alignment); } } - - /* The depth and stencil buffers are in separate resources on evergreen. - * We allocate them in one buffer next to each other to simplify - * communication between the DDX and the Mesa driver. */ - if ((surf->flags & (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)) == - (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)) { - surf->stencil_offset = ALIGN(surf->bo_size, surf->bo_alignment); - surf->bo_size = surf->stencil_offset + surf->bo_size / 4; - } - return 0; } -- To UNSUBSCRIBE, email to [email protected] with a subject of "unsubscribe". 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