debian/changelog | 9 + debian/patches/series | 3 debian/patches/skl-implement-wadisable1ddepthstencil.diff | 38 ++++++++ debian/patches/skl-use-1-register-for-uniform-pull.diff | 35 +++++++ debian/patches/skl-use-vec4-datatypes-for-message-header.diff | 47 ++++++++++ 5 files changed, 132 insertions(+)
New commits: commit 17d6ea29000d4bf1899a9f95d8f8b5e4efd1560e Author: Timo Aaltonen <[email protected]> Date: Tue Feb 24 14:33:13 2015 +0200 Add a couple of backported fixes for Skylake skl-use-1-register-for-uniform-pull.diff skl-use-vec4-datatypes-for-message-header.diff skl-implement-wadisable1ddepthstencil.diff diff --git a/debian/changelog b/debian/changelog index f51097a..4443960 100644 --- a/debian/changelog +++ b/debian/changelog @@ -1,3 +1,12 @@ +mesa (10.5.0~rc1-0ubuntu2) vivid; urgency=medium + + * Add a couple of backported fixes for Skylake: + skl-use-1-register-for-uniform-pull.diff + skl-use-vec4-datatypes-for-message-header.diff + skl-implement-wadisable1ddepthstencil.diff + + -- Timo Aaltonen <[email protected]> Fri, 20 Feb 2015 08:54:44 +0200 + mesa (10.5.0~rc1-0ubuntu1) vivid; urgency=medium [ Timo Aaltonen ] diff --git a/debian/patches/series b/debian/patches/series index af4c631..21442ad 100644 --- a/debian/patches/series +++ b/debian/patches/series @@ -3,3 +3,6 @@ # Ubuntu patches. egl-platform-mir.patch i915-dont-default-to-2.1.patch +skl-use-1-register-for-uniform-pull.diff +skl-use-vec4-datatypes-for-message-header.diff +skl-implement-wadisable1ddepthstencil.diff diff --git a/debian/patches/skl-implement-wadisable1ddepthstencil.diff b/debian/patches/skl-implement-wadisable1ddepthstencil.diff new file mode 100644 index 0000000..13e6534 --- /dev/null +++ b/debian/patches/skl-implement-wadisable1ddepthstencil.diff @@ -0,0 +1,38 @@ +commit 5b29b2922afe2b8167a589fc2896a071fc85b693 +Author: Neil Roberts <[email protected]> +Date: Mon Feb 2 17:47:23 2015 +0000 + + i965/skl: Implement WaDisable1DDepthStencil + + Skylake+ doesn't support setting a depth buffer to a 1D surface but it + does allow pretending it's a 2D texture with a height of 1 instead. + + This fixes the GL_DEPTH_COMPONENT_* tests of the copyteximage piglit + test (and also seems to avoid a subsequent GPU hang). + + Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89037 + Reviewed-by: Kenneth Graunke <[email protected]> + +diff --git a/src/mesa/drivers/dri/i965/gen8_depth_state.c b/src/mesa/drivers/dri/i965/gen8_depth_state.c +index e428089..b4eb6e1 100644 +--- a/src/mesa/drivers/dri/i965/gen8_depth_state.c ++++ b/src/mesa/drivers/dri/i965/gen8_depth_state.c +@@ -190,6 +190,18 @@ gen8_emit_depth_stencil_hiz(struct brw_context *brw, + case GL_TEXTURE_3D: + assert(mt); + depth = MAX2(mt->logical_depth0, 1); ++ surftype = translate_tex_target(gl_target); ++ break; ++ case GL_TEXTURE_1D_ARRAY: ++ case GL_TEXTURE_1D: ++ if (brw->gen >= 9) { ++ /* WaDisable1DDepthStencil. Skylake+ doesn't support 1D depth ++ * textures but it does allow pretending it's a 2D texture ++ * instead. ++ */ ++ surftype = BRW_SURFACE_2D; ++ break; ++ } + /* fallthrough */ + default: + surftype = translate_tex_target(gl_target); diff --git a/debian/patches/skl-use-1-register-for-uniform-pull.diff b/debian/patches/skl-use-1-register-for-uniform-pull.diff new file mode 100644 index 0000000..a89cbc4 --- /dev/null +++ b/debian/patches/skl-use-1-register-for-uniform-pull.diff @@ -0,0 +1,35 @@ +From 5255e1a9e6599942b10724fe5e573979f123b7e0 Mon Sep 17 00:00:00 2001 +From: Ben Widawsky <[email protected]> +Date: Thu, 19 Feb 2015 15:49:34 -0800 +Subject: [PATCH] i965/skl: Use 1 register for uniform pull constant payload + +When under dispatch_width=16 the previous code would allocate 2 registers for +the payload when only one is needed. This manifested itself through bugs on SKL +which needs to mess with this instruction. + +Ken says this might have some positive impact on shader-db. + +Cc: Kenneth Graunke <[email protected]> +Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89118 +Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88999 +Signed-off-by: Ben Widawsky <[email protected]> +--- + src/mesa/drivers/dri/i965/brw_fs.cpp | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp +index a562b8a..bb647bd 100644 +--- a/src/mesa/drivers/dri/i965/brw_fs.cpp ++++ b/src/mesa/drivers/dri/i965/brw_fs.cpp +@@ -3062,7 +3062,7 @@ fs_visitor::lower_uniform_pull_constant_loads() + assert(const_offset_reg.file == IMM && + const_offset_reg.type == BRW_REGISTER_TYPE_UD); + const_offset_reg.fixed_hw_reg.dw1.ud /= 4; +- fs_reg payload = vgrf(glsl_type::uint_type); ++ fs_reg payload = fs_reg(GRF, virtual_grf_alloc(1)); + + /* We have to use a message header on Skylake to get SIMD4x2 mode. + * Reserve space for the register. +-- +2.3.0 + diff --git a/debian/patches/skl-use-vec4-datatypes-for-message-header.diff b/debian/patches/skl-use-vec4-datatypes-for-message-header.diff new file mode 100644 index 0000000..26d3608 --- /dev/null +++ b/debian/patches/skl-use-vec4-datatypes-for-message-header.diff @@ -0,0 +1,47 @@ +commit e93566a15c61c33faa2e694aa18d18e544e857ff +Author: Ben Widawsky <[email protected]> +Date: Tue Feb 10 17:22:45 2015 -0800 + + i965/vs/skl: Use vec4 datatypes for message header + + We're using a SIMD4x2 sampler message, which has execsize 4, and so the + register width must be <= 4. Use <4,4,1> regioning instead of <8,8,1> + regioning to access the same data but avoid tripping the assert. + + Fixes the following piglit tests: + spec/glsl-1.20/compiler/structure-and-array-operations/array-selection.vert + spec/glsl-es-3.00/compiler/uniform_block/interface-name-basic.vert + spec/glsl-es-3.00/compiler/uniform_block/interface-name-field-clashes-with-struct.vert + spec/glsl-es-3.00/compiler/uniform_block/interface-name-field-clashes-with-function.vert + spec/glsl-es-3.00/compiler/uniform_block/interface-name-array.vert + glslparsertest/glsl2/condition-07.vert + spec/glsl-es-3.00/compiler/uniform_block/interface-name-field-clashes-with-variable.vert + + v2: Better commit message courtesy of Ken. + I had a discussion with Ken, and we both question how we end up with a mov and + execsize 4. For now though, this fixes the piglit tests, so we can worry about + it later. + + Signed-off-by: Ben Widawsky <[email protected]> + Reviewed-by: Kenneth Graunke <[email protected]> + +diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp +index 8cd36f8..f7b8771 100644 +--- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp ++++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp +@@ -1024,13 +1024,13 @@ fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst *inst, + + if (brw->gen >= 9) { + /* Skylake requires a message header in order to use SIMD4x2 mode. */ +- src = retype(brw_vec8_grf(offset.nr - 1, 0), BRW_REGISTER_TYPE_UD); ++ src = retype(brw_vec4_grf(offset.nr - 1, 0), BRW_REGISTER_TYPE_UD); + mlen = 2; + header_present = true; + + brw_push_insn_state(p); + brw_set_default_mask_control(p, BRW_MASK_DISABLE); +- brw_MOV(p, src, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)); ++ brw_MOV(p, src, retype(brw_vec4_grf(0, 0), BRW_REGISTER_TYPE_UD)); + brw_set_default_access_mode(p, BRW_ALIGN_1); + + brw_MOV(p, get_element_ud(src, 2), -- To UNSUBSCRIBE, email to [email protected] with a subject of "unsubscribe". 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