VERSION | 2
bin/.cherry-ignore | 6
debian/changelog | 13
debian/upstream/signing-key.asc | 76 ++++
docs/relnotes/17.0.2.html | 3
docs/relnotes/17.0.3.html | 188 ++++++++++++
include/c11/threads.h | 5
include/pci_ids/radeonsi_pci_ids.h | 1
src/amd/vulkan/radv_cmd_buffer.c | 8
src/compiler/glsl/linker.cpp | 6
src/compiler/glsl/lower_jumps.cpp | 17 -
src/compiler/glsl/tests/cache_test.c | 2
src/compiler/glsl/tests/lower_jumps/create_test_cases.py | 17 -
src/gallium/drivers/freedreno/freedreno_draw.c | 2
src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp | 1
src/gallium/drivers/radeonsi/si_state_shaders.c | 2
src/gallium/drivers/swr/rasterizer/jitter/blend_jit.cpp | 2
src/gallium/drivers/swr/rasterizer/jitter/fetch_jit.cpp | 2
src/gallium/drivers/swr/rasterizer/jitter/streamout_jit.cpp | 2
src/gallium/state_trackers/clover/core/resource.cpp | 11
src/gallium/state_trackers/clover/core/resource.hpp | 1
src/gallium/state_trackers/nine/nine_csmt_helper.h | 2
src/gallium/state_trackers/nine/resource9.c | 4
src/gallium/state_trackers/nine/surface9.c | 10
src/gallium/state_trackers/nine/volume9.c | 10
src/intel/isl/isl.c | 2
src/intel/vulkan/anv_blorp.c | 24 -
src/intel/vulkan/anv_image.c | 9
src/intel/vulkan/anv_private.h | 13
src/intel/vulkan/anv_query.c | 60 ++-
src/intel/vulkan/genX_cmd_buffer.c | 59 ++-
src/intel/vulkan/genX_pipeline.c | 4
src/mesa/drivers/dri/i965/brw_fs_sel_peephole.cpp | 2
src/mesa/drivers/dri/i965/brw_misc_state.c | 3
src/mesa/drivers/dri/i965/gen8_surface_state.c | 5
src/mesa/drivers/dri/i965/intel_screen.c | 11
src/mesa/main/api_validate.c | 24 +
src/mesa/main/api_validate.h | 2
src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 1
39 files changed, 509 insertions(+), 103 deletions(-)
New commits:
commit 809c1bc9234f72afc82ec4ac69b2487cf8f4baf0
Author: Timo Aaltonen <tjaal...@debian.org>
Date: Mon Apr 3 19:20:25 2017 +0300
upload to zesty
diff --git a/debian/changelog b/debian/changelog
index 7378622..e6ff8a8 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,3 +1,9 @@
+mesa (17.0.3-1ubuntu1) zesty; urgency=medium
+
+ * Merge from Debian.
+
+ -- Timo Aaltonen <tjaal...@debian.org> Mon, 03 Apr 2017 19:03:10 +0300
+
mesa (17.0.3-1) experimental; urgency=medium
* New upstream release.
commit 4a3a6cb8fabd56a18ab9085d114bd13b3bf0e3a1
Author: Andreas Boll <andreas.boll....@gmail.com>
Date: Mon Apr 3 11:36:17 2017 +0200
Upload to experimental.
diff --git a/debian/changelog b/debian/changelog
index b7ba713..0c014d1 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,9 +1,9 @@
-mesa (17.0.3-1) UNRELEASED; urgency=medium
+mesa (17.0.3-1) experimental; urgency=medium
* New upstream release.
* Update d/upstream/signing-key.asc with key from Andres Gomez.
- -- Andreas Boll <andreas.boll....@gmail.com> Mon, 03 Apr 2017 10:10:35 +0200
+ -- Andreas Boll <andreas.boll....@gmail.com> Mon, 03 Apr 2017 11:35:58 +0200
mesa (17.0.2-1) experimental; urgency=medium
commit cabb4251658368c8104f9c57e8bd7ff0ed576996
Author: Andreas Boll <andreas.boll....@gmail.com>
Date: Mon Apr 3 10:11:46 2017 +0200
Update d/upstream/signing-key.asc with key from Andres Gomez.
diff --git a/debian/changelog b/debian/changelog
index a007454..b7ba713 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,6 +1,7 @@
mesa (17.0.3-1) UNRELEASED; urgency=medium
* New upstream release.
+ * Update d/upstream/signing-key.asc with key from Andres Gomez.
-- Andreas Boll <andreas.boll....@gmail.com> Mon, 03 Apr 2017 10:10:35 +0200
diff --git a/debian/upstream/signing-key.asc b/debian/upstream/signing-key.asc
index 360f6c8..797c071 100644
--- a/debian/upstream/signing-key.asc
+++ b/debian/upstream/signing-key.asc
@@ -616,3 +616,79 @@
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T0rEAQLWU7eq9U6nd4BXMkokiuzlOKWqsDyXibR3wkhI80kAJw==
=XSpT
-----END PGP PUBLIC KEY BLOCK-----
+-----BEGIN PGP PUBLIC KEY BLOCK-----
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commit d47e8b02066ec910b8ef14c90bf0958ac3858190
Author: Andreas Boll <andreas.boll....@gmail.com>
Date: Mon Apr 3 10:10:51 2017 +0200
Bump changelog
diff --git a/debian/changelog b/debian/changelog
index 3959bee..a007454 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,3 +1,9 @@
+mesa (17.0.3-1) UNRELEASED; urgency=medium
+
+ * New upstream release.
+
+ -- Andreas Boll <andreas.boll....@gmail.com> Mon, 03 Apr 2017 10:10:35 +0200
+
mesa (17.0.2-1) experimental; urgency=medium
[ Timo Aaltonen ]
commit 7f34ecae7fddd3435346f0475557b34920763422
Author: Andres Gomez <ago...@igalia.com>
Date: Sat Apr 1 17:29:34 2017 +0300
docs: add release notes for 17.0.3
Signed-off-by: Andres Gomez <ago...@igalia.com>
diff --git a/docs/relnotes/17.0.3.html b/docs/relnotes/17.0.3.html
new file mode 100644
index 0000000..64efe0b
--- /dev/null
+++ b/docs/relnotes/17.0.3.html
@@ -0,0 +1,188 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN"
"http://www.w3.org/TR/html4/loose.dtd";>
+<html lang="en">
+<head>
+ <meta http-equiv="content-type" content="text/html; charset=utf-8">
+ <title>Mesa Release Notes</title>
+ <link rel="stylesheet" type="text/css" href="../mesa.css">
+</head>
+<body>
+
+<div class="header">
+ <h1>The Mesa 3D Graphics Library</h1>
+</div>
+
+<iframe src="../contents.html"></iframe>
+<div class="content">
+
+<h1>Mesa 17.0.3 Release Notes / April 1, 2017</h1>
+
+<p>
+Mesa 17.0.3 is a bug fix release which fixes bugs found since the 17.0.2
release.
+</p>
+<p>
+Mesa 17.0.3 implements the OpenGL 4.5 API, but the version reported by
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 4.5. OpenGL
+4.5 is <strong>only</strong> available if requested at context creation
+because compatibility contexts are not supported.
+</p>
+
+
+<h2>SHA256 checksums</h2>
+<pre>
+TBD
+</pre>
+
+
+<h2>New features</h2>
+<p>None</p>
+
+
+<h2>Bug fixes</h2>
+
+<ul>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=96743";>Bug 96743</a>
- [BYT, HSW, SKL, BXT, KBL] GPU hangs with GfxBench 4.0 CarChase</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=99246";>Bug 99246</a>
- [d3dadapter+radeonsi & bisect] EVE-Online : hang on wormhole sight</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=100061";>Bug
100061</a> - LODQ instruction generated with invalid dst mask</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=100182";>Bug
100182</a> - Flickering in The Talos Principle on Sky Lake GT4.</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=100201";>Bug
100201</a> - Windows scons build with MSVC toolchain and LLVM 4.0 fails</li>
+
+</ul>
+
+
+<h2>Changes</h2>
+
+<p>Alex Deucher (1):</p>
+<ul>
+ <li>radeonsi: add new polaris12 pci id</li>
+</ul>
+
+<p>Andres Gomez (5):</p>
+<ul>
+ <li>glsl: on UBO/SSBOs link error reset the number of active blocks to 0</li>
+ <li>cherry-ignore: add the Invalidate L2 for TRANSFER_WRITE barriers fix</li>
+ <li>cherry-ignore: add the Flush after unmap in gbm/dri fix</li>
+ <li>cherry-ignore: corrected typo in the Flush after unmap in gbm/dri
fix</li>
+ <li>Update version to 17.0.3</li>
+</ul>
+
+<p>Axel Davy (2):</p>
+<ul>
+ <li>st/nine: Resolve deadlock in surface/volume dtors when using csmt</li>
+ <li>st/nine: Use atomics for available_texture_mem</li>
+</ul>
+
+<p>Bas Nieuwenhuizen (1):</p>
+<ul>
+ <li>radv: flush DB cache before and after HTILE decompress.</li>
+</ul>
+
+<p>Dave Airlie (1):</p>
+<ul>
+ <li>radv: fix primitive reset index emission</li>
+</ul>
+
+<p>Emil Velikov (1):</p>
+<ul>
+ <li>docs: add sha256 checksums for 17.0.2</li>
+</ul>
+
+<p>Ilia Mirkin (1):</p>
+<ul>
+ <li>st/mesa: set result writemask based on ir type</li>
+</ul>
+
+<p>Jan Vesely (1):</p>
+<ul>
+ <li>clover: use pipe_resource references</li>
+</ul>
+
+<p>Jason Ekstrand (9):</p>
+<ul>
+ <li>anv/query: Invalidate the correct range</li>
+ <li>anv/GetQueryPoolResults: Actually implement the spec</li>
+ <li>anv/image: Return early when unbinding an image</li>
+ <li>anv/query: Fix the location of timestamp availability</li>
+ <li>anv: Make anv_get_layerCount a macro</li>
+ <li>anv/blorp: Use anv_get_layerCount everywhere</li>
+ <li>anv/cmd_buffer: Apply flush operations prior to executing
secondaries</li>
+ <li>anv/cmd_buffer: Fix bad indentation</li>
+ <li>anv: Flush caches prior to PIPELINE_SELECT on all gens</li>
+</ul>
+
+<p>José Fonseca (1):</p>
+<ul>
+ <li>c11/threads: Include thr/xtimec.h for xtime definition when building
with MSVC.</li>
+</ul>
+
+<p>Juan A. Suarez Romero (1):</p>
+<ul>
+ <li>tests/cache_test: allow crossing mount points</li>
+</ul>
+
+<p>Karol Herbst (1):</p>
+<ul>
+ <li>nvc0/ir: treat FMA like MAD for operand propagation</li>
+</ul>
+
+<p>Kenneth Graunke (1):</p>
+<ul>
+ <li>i965: Fall back to GL 4.2/4.3 on Haswell if the kernel isn't new
enough.</li>
+</ul>
+
+<p>Marek Olšák (1):</p>
+<ul>
+ <li>radeonsi: don't hang on shader compile failure</li>
+</ul>
+
+<p>Matt Turner (1):</p>
+<ul>
+ <li>i965/fs: Don't emit SEL instructions for type-converting MOVs.</li>
+</ul>
+
+<p>Nanley Chery (1):</p>
+<ul>
+ <li>intel: Correct the BDW surface state size</li>
+</ul>
+
+<p>Nicolai Hähnle (1):</p>
+<ul>
+ <li>mesa/main: fix MultiDrawElements[BaseVertex] validation of primcount</li>
+</ul>
+
+<p>Rob Clark (1):</p>
+<ul>
+ <li>freedreno: fix memory leak</li>
+</ul>
+
+<p>Tim Rowley (1):</p>
+<ul>
+ <li>swr: [rasterizer jitter] fix llvm >= 5.0 build break</li>
+</ul>
+
+<p>Timothy Arceri (2):</p>
+<ul>
+ <li>glsl: fix lower jumps for returns when loop is inside an if</li>
+ <li>mesa: update lower_jumps tests after bug fix</li>
+</ul>
+
+<p>Topi Pohjolainen (1):</p>
+<ul>
+ <li>i965/gen8+: Do full stall when switching pipeline</li>
+</ul>
+
+<p>Xu Randy (2):</p>
+<ul>
+ <li>anv/blorp: Fix a crash in CmdClearColorImage</li>
+ <li>anv/genX: Solve the vkCreateGraphicsPipelines crash</li>
+</ul>
+
+</div>
+</body>
+</html>
commit 3a90fc5717b693e0fbe04c6b2e04bba93f494f72
Author: Andres Gomez <ago...@igalia.com>
Date: Sat Apr 1 15:12:39 2017 +0300
Update version to 17.0.3
Signed-off-by: Andres Gomez <ago...@igalia.com>
diff --git a/VERSION b/VERSION
index c57cf9a..cc64c91 100644
--- a/VERSION
+++ b/VERSION
@@ -1 +1 @@
-17.0.2
+17.0.3
commit fd3b756abbbfc1f9a25a564aaad0bef110c666f8
Author: Andres Gomez <ago...@igalia.com>
Date: Thu Mar 30 23:45:49 2017 +0300
cherry-ignore: corrected typo in the Flush after unmap in gbm/dri fix
The regression was for i915, not i965.
Signed-off-by: Andres Gomez <ago...@igalia.com>
diff --git a/bin/.cherry-ignore b/bin/.cherry-ignore
index aac17de..d97ff39 100644
--- a/bin/.cherry-ignore
+++ b/bin/.cherry-ignore
@@ -3,6 +3,6 @@ d49d275c415d60ae08dc3e52d8db11f19a44010f anv/blorp: Don't
sanitize the swizzle f
# The commit addressed an earlier commit 0567ab0407e which did not land in
branch.
# A stable specific backported patch will follow later ...
bc5d587a80b64fb3e0a5ea8067e6317fbca2bbc5 radv: Invalidate L2 for
TRANSFER_WRITE barriers
-# The commit caused a regression in i965 (and possibly others) since
+# The commit caused a regression in i915 (and possibly others) since
# it didn't implement v4 of DRI2's flush extension.
ba8df2286a50117011925e915cd832b4a79f126e gbm/dri: Flush after unmap
commit 3a84f6fd4330a00a8d89c24d569dbb450832602d
Author: Andres Gomez <ago...@igalia.com>
Date: Thu Mar 30 16:48:24 2017 +0300
cherry-ignore: add the Flush after unmap in gbm/dri fix
The commit caused a regression in i965 (and possibly others) since it
didn't implement v4 of DRI2's flush extension.
Signed-off-by: Andres Gomez <ago...@igalia.com>
diff --git a/bin/.cherry-ignore b/bin/.cherry-ignore
index 0bb90e2..aac17de 100644
--- a/bin/.cherry-ignore
+++ b/bin/.cherry-ignore
@@ -3,3 +3,6 @@ d49d275c415d60ae08dc3e52d8db11f19a44010f anv/blorp: Don't
sanitize the swizzle f
# The commit addressed an earlier commit 0567ab0407e which did not land in
branch.
# A stable specific backported patch will follow later ...
bc5d587a80b64fb3e0a5ea8067e6317fbca2bbc5 radv: Invalidate L2 for
TRANSFER_WRITE barriers
+# The commit caused a regression in i965 (and possibly others) since
+# it didn't implement v4 of DRI2's flush extension.
+ba8df2286a50117011925e915cd832b4a79f126e gbm/dri: Flush after unmap
commit 57904e481f4b3baec7ff8bfa2a106349266409b8
Author: Andres Gomez <ago...@igalia.com>
Date: Wed Mar 29 01:24:24 2017 +0300
cherry-ignore: add the Invalidate L2 for TRANSFER_WRITE barriers fix
Addressed an earlier commit [0567ab0407e] which did not land in
branch. This will be backported with a stable specific patch.
Signed-off-by: Andres Gomez <ago...@igalia.com>
diff --git a/bin/.cherry-ignore b/bin/.cherry-ignore
index 7121f14..0bb90e2 100644
--- a/bin/.cherry-ignore
+++ b/bin/.cherry-ignore
@@ -1,2 +1,5 @@
# The commit addressed an earlier commit ccdd5b3738e which did not land in
branch.
d49d275c415d60ae08dc3e52d8db11f19a44010f anv/blorp: Don't sanitize the swizzle
for blorp_clear
+# The commit addressed an earlier commit 0567ab0407e which did not land in
branch.
+# A stable specific backported patch will follow later ...
+bc5d587a80b64fb3e0a5ea8067e6317fbca2bbc5 radv: Invalidate L2 for
TRANSFER_WRITE barriers
commit 3d59fd83ed128d48c15b4e0f2c7a9bcf6d6f6566
Author: Jose Fonseca <jfons...@vmware.com>
Date: Tue Mar 28 11:25:04 2017 +0100
c11/threads: Include thr/xtimec.h for xtime definition when building with
MSVC.
MSVC has been including a xtime definition in thr/xtimec.h ever since
MSVC 2013 (which is the minimum we require for building Mesa), and
including it prevents duplicate definitions when it gets included by
LLVM.
In fact, it looks that MSVC has been including a partial C11 threads
implementation too for some time, which we should consider migrating to
once we eliminate the use of _MTX_INITIALIZER_NP in our tree.
Thanks to the anonymous helper from
https://bugs.freedesktop.org/show_bug.cgi?id=100201#c4 for spotting
this.
Reviewed-by: Roland Scheidegger <srol...@vmware.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100201
CC: "17.0" <mesa-sta...@lists.freedesktop.org>
(cherry picked from commit ecfafdcbf51d8919e219539b57ffbd9cd3f8557a)
diff --git a/include/c11/threads.h b/include/c11/threads.h
index 45823df..573348d 100644
--- a/include/c11/threads.h
+++ b/include/c11/threads.h
@@ -30,6 +30,9 @@
#define EMULATED_THREADS_H_INCLUDED_
#include <time.h>
+#ifdef _MSC_VER
+#include <thr/xtimec.h> // for xtime
+#endif
#ifndef TIME_UTC
#define TIME_UTC 1
@@ -41,11 +44,13 @@
typedef void (*tss_dtor_t)(void*);
typedef int (*thrd_start_t)(void*);
+#ifndef _MSC_VER
struct xtime {
time_t sec;
long nsec;
};
typedef struct xtime xtime;
+#endif
/*-------------------- enumeration constants --------------------*/
commit 9caf60b3a2c25d46c78c9cdba36e663b687ffd50
Author: Jason Ekstrand <ja...@jlekstrand.net>
Date: Wed Mar 15 11:58:52 2017 -0700
anv: Flush caches prior to PIPELINE_SELECT on all gens
The programming note that says we need to do this still exists in the
SkyLake PRM and, from looking at the bspec, seems like it may apply to
all hardware generations SNB+. Unfortunately, this isn't particularly
clear cut since there is also language in the bspec that says you can
skip the flushing and stall to get better throughput. Experimentation
with the "Car Chase" benchmark in GL seems to indicate that some form of
flushing is still needed. This commit makes us do the full set of
flushes regardless of hardware generation. We can always reduce the
flushing later.
Reported-by: Topi Pohjolainen <topi.pohjolai...@intel.com>
Reviewed-by: Iago Toral Quiroga <ito...@igalia.com>
Cc: "17.0 13.0" <mesa-sta...@lists.freedesktop.org>
(cherry picked from commit 6baae9625d26d282a72481598f9431fcad3211f6)
diff --git a/src/intel/vulkan/genX_cmd_buffer.c
b/src/intel/vulkan/genX_cmd_buffer.c
index 0a20780..ac38ec8 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -2033,8 +2033,8 @@ flush_pipeline_before_pipeline_select(struct
anv_cmd_buffer *cmd_buffer,
*/
if (pipeline == GPGPU)
anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_CC_STATE_POINTERS), t);
+#endif
-#elif GEN_GEN <= 7
/* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
* PIPELINE_SELECT [DevBWR+]":
*
@@ -2060,7 +2060,6 @@ flush_pipeline_before_pipeline_select(struct
anv_cmd_buffer *cmd_buffer,
pc.InstructionCacheInvalidateEnable = true;
pc.PostSyncOperation = NoWrite;
}
-#endif
}
void
commit 1761f9d4b2f5a3ed5092a9fef390d5ae5cc07411
Author: Jason Ekstrand <ja...@jlekstrand.net>
Date: Wed Mar 15 11:58:51 2017 -0700
anv/cmd_buffer: Fix bad indentation
A bunch of code was indented in such a way that it looked like it went
with the if statement above but it definitely didn't.
Reviewed-by: Iago Toral Quiroga <ito...@igalia.com>
Cc: "17.0 13.0" <mesa-sta...@lists.freedesktop.org>
(cherry picked from commit 0fe3dcce4c3e8b86a60beefe4c5adc760f2d59f8)
diff --git a/src/intel/vulkan/genX_cmd_buffer.c
b/src/intel/vulkan/genX_cmd_buffer.c
index db212c4..0a20780 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -2033,32 +2033,33 @@ flush_pipeline_before_pipeline_select(struct
anv_cmd_buffer *cmd_buffer,
*/
if (pipeline == GPGPU)
anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_CC_STATE_POINTERS), t);
+
#elif GEN_GEN <= 7
- /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
- * PIPELINE_SELECT [DevBWR+]":
- *
- * Project: DEVSNB+
- *
- * Software must ensure all the write caches are flushed through a
- * stalling PIPE_CONTROL command followed by another PIPE_CONTROL
- * command to invalidate read only caches prior to programming
- * MI_PIPELINE_SELECT command to change the Pipeline Select Mode.
- */
- anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
- pc.RenderTargetCacheFlushEnable = true;
- pc.DepthCacheFlushEnable = true;
- pc.DCFlushEnable = true;
- pc.PostSyncOperation = NoWrite;
- pc.CommandStreamerStallEnable = true;
- }
+ /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
+ * PIPELINE_SELECT [DevBWR+]":
+ *
+ * Project: DEVSNB+
+ *
+ * Software must ensure all the write caches are flushed through a
+ * stalling PIPE_CONTROL command followed by another PIPE_CONTROL
+ * command to invalidate read only caches prior to programming
+ * MI_PIPELINE_SELECT command to change the Pipeline Select Mode.
+ */
+ anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
+ pc.RenderTargetCacheFlushEnable = true;
+ pc.DepthCacheFlushEnable = true;
+ pc.DCFlushEnable = true;
+ pc.PostSyncOperation = NoWrite;
+ pc.CommandStreamerStallEnable = true;
+ }
- anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
- pc.TextureCacheInvalidationEnable = true;
- pc.ConstantCacheInvalidationEnable = true;
- pc.StateCacheInvalidationEnable = true;
- pc.InstructionCacheInvalidateEnable = true;
- pc.PostSyncOperation = NoWrite;
- }
+ anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
+ pc.TextureCacheInvalidationEnable = true;
+ pc.ConstantCacheInvalidationEnable = true;
+ pc.StateCacheInvalidationEnable = true;
+ pc.InstructionCacheInvalidateEnable = true;
+ pc.PostSyncOperation = NoWrite;
+ }
#endif
}
commit 9973db02a04621598bf504fcc7797522ee5046de
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Fri Mar 24 16:30:24 2017 -0700
anv/cmd_buffer: Apply flush operations prior to executing secondaries
This fixes rendering issues in the Vulkan port of skia on some hardware.
Reviewed-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Cc: "13.0 17.0" <mesa-sta...@lists.freedesktop.org>
(cherry picked from commit 01a65dc43be3a4bf6b8a901586f7222218f4b6b3)
[Andres Gomez: resolve trivial conflicts]
Signed-off-by: Andres Gomez <ago...@igalia.com>
Conflicts:
src/intel/vulkan/genX_cmd_buffer.c
diff --git a/src/intel/vulkan/genX_cmd_buffer.c
b/src/intel/vulkan/genX_cmd_buffer.c
index 320b050..db212c4 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -643,6 +643,11 @@ genX(CmdExecuteCommands)(
assert(primary->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
+ /* The secondary command buffer doesn't know which textures etc. have been
+ * flushed prior to their execution. Apply those flushes now.
+ */
+ genX(cmd_buffer_apply_pipe_flushes)(primary);
+
for (uint32_t i = 0; i < commandBufferCount; i++) {
ANV_FROM_HANDLE(anv_cmd_buffer, secondary, pCmdBuffers[i]);
commit 0a9e06e5b911f19bca3a826f6d4d7cf038e2f823
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Fri Mar 24 16:20:35 2017 -0700
anv/blorp: Use anv_get_layerCount everywhere
Reviewed-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Cc: "13.0 17.0" <mesa-sta...@lists.freedesktop.org>
(cherry picked from commit 9319ef96fd5c2489754eae1b058e4087d7259341)
diff --git a/src/intel/vulkan/anv_blorp.c b/src/intel/vulkan/anv_blorp.c
index dde0d96..42fce6f 100644
--- a/src/intel/vulkan/anv_blorp.c
+++ b/src/intel/vulkan/anv_blorp.c
@@ -227,7 +227,8 @@ void anv_CmdCopyImage(
layer_count = pRegions[r].extent.depth;
} else {
dst_base_layer = pRegions[r].dstSubresource.baseArrayLayer;
- layer_count = pRegions[r].dstSubresource.layerCount;
+ layer_count =
+ anv_get_layerCount(dst_image, &pRegions[r].dstSubresource);
}
unsigned src_base_layer;
@@ -235,7 +236,8 @@ void anv_CmdCopyImage(
src_base_layer = pRegions[r].srcOffset.z;
} else {
src_base_layer = pRegions[r].srcSubresource.baseArrayLayer;
- assert(pRegions[r].srcSubresource.layerCount == layer_count);
+ assert(layer_count ==
+ anv_get_layerCount(src_image, &pRegions[r].srcSubresource));
}
assert(pRegions[r].srcSubresource.aspectMask ==
@@ -307,7 +309,8 @@ copy_buffer_to_image(struct anv_cmd_buffer *cmd_buffer,
anv_sanitize_image_extent(anv_image->type, pRegions[r].imageExtent);
if (anv_image->type != VK_IMAGE_TYPE_3D) {
image.offset.z = pRegions[r].imageSubresource.baseArrayLayer;
- extent.depth = pRegions[r].imageSubresource.layerCount;
+ extent.depth =
+ anv_get_layerCount(anv_image, &pRegions[r].imageSubresource);
}
const enum isl_format buffer_format =
@@ -461,7 +464,7 @@ void anv_CmdBlitImage(
dst_end = pRegions[r].dstOffsets[1].z;
} else {
dst_start = dst_res->baseArrayLayer;
- dst_end = dst_start + dst_res->layerCount;
+ dst_end = dst_start + anv_get_layerCount(dst_image, dst_res);
}
unsigned src_start, src_end;
@@ -471,7 +474,7 @@ void anv_CmdBlitImage(
src_end = pRegions[r].srcOffsets[1].z;
} else {
src_start = src_res->baseArrayLayer;
- src_end = src_start + src_res->layerCount;
+ src_end = src_start + anv_get_layerCount(src_image, src_res);
}
bool flip_z = flip_coords(&src_start, &src_end, &dst_start, &dst_end);
@@ -1379,10 +1382,11 @@ void anv_CmdResolveImage(
for (uint32_t r = 0; r < regionCount; r++) {
assert(pRegions[r].srcSubresource.aspectMask ==
pRegions[r].dstSubresource.aspectMask);
- assert(pRegions[r].srcSubresource.layerCount ==
- pRegions[r].dstSubresource.layerCount);
+ assert(anv_get_layerCount(src_image, &pRegions[r].srcSubresource) ==
+ anv_get_layerCount(dst_image, &pRegions[r].dstSubresource));
- const uint32_t layer_count = pRegions[r].dstSubresource.layerCount;
+ const uint32_t layer_count =
+ anv_get_layerCount(dst_image, &pRegions[r].dstSubresource);
for (uint32_t layer = 0; layer < layer_count; layer++) {
resolve_image(&batch,
commit 6cabd40211413bbf780fa61949da7dde47608792
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Fri Mar 24 16:20:18 2017 -0700
anv: Make anv_get_layerCount a macro
Reviewed-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Cc: "13.0 17.0" <mesa-sta...@lists.freedesktop.org>
(cherry picked from commit 1b8fa8dd794c22aba43b16470e75ecaebf902b11)
[Andres Gomez: resolve trivial conflicts]
Signed-off-by: Andres Gomez <ago...@igalia.com>
Conflicts:
src/intel/vulkan/anv_private.h
diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
index 52e6ed5..d3e79df 100644
--- a/src/intel/vulkan/anv_private.h
+++ b/src/intel/vulkan/anv_private.h
@@ -1627,13 +1627,12 @@ anv_gen8_hiz_op_resolve(struct anv_cmd_buffer
*cmd_buffer,
const struct anv_image *image,
enum blorp_hiz_op op);
-static inline uint32_t
-anv_get_layerCount(const struct anv_image *image,
- const VkImageSubresourceRange *range)
-{
- return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
- image->array_size - range->baseArrayLayer : range->layerCount;
-}
+/* This is defined as a macro so that it works for both
+ * VkImageSubresourceRange and VkImageSubresourceLayers
+ */
+#define anv_get_layerCount(_image, _range) \
+ ((_range)->layerCount == VK_REMAINING_ARRAY_LAYERS ? \
+ (_image)->array_size - (_range)->baseArrayLayer : (_range)->layerCount)
static inline uint32_t
anv_get_levelCount(const struct anv_image *image,
commit 4b3fddaa1aeba342e2e2551558b6867b13789de5
Author: Timothy Arceri <tarc...@itsqueeze.com>
Date: Wed Mar 29 20:30:19 2017 +1100
mesa: update lower_jumps tests after bug fix
This change updates the tests to reflect the IR after
the following bug fix.
Fixes: c1096b7f1d49 ("glsl: fix lower jumps for returns when loop is
inside an if")
Tested-by: Michel Dänzer <michel.daen...@amd.com>
Bugzilla: https://bugs.freedesktop.org/100441
(cherry picked from commit e44cba540ee7a07bba643bab4b9e519e90244bd1)
diff --git a/src/compiler/glsl/tests/lower_jumps/create_test_cases.py
b/src/compiler/glsl/tests/lower_jumps/create_test_cases.py
index 3be1079..ceb64a3 100644
--- a/src/compiler/glsl/tests/lower_jumps/create_test_cases.py
+++ b/src/compiler/glsl/tests/lower_jumps/create_test_cases.py
@@ -236,6 +236,13 @@ def if_execute_flag(statements):
check_sexp(statements)
return [['if', ['var_ref', 'execute_flag'], statements, []]]
+def if_return_flag(then_statements, else_statements):
+ """Wrap statements in an if test with return_flag as the condition.
+ """
+ check_sexp(then_statements)
+ check_sexp(else_statements)
+ return [['if', ['var_ref', 'return_flag'], then_statements,
else_statements]]
+
def if_not_return_flag(statements):
"""Wrap statements in an if test so that they will only execute if
return_flag is False.
@@ -452,7 +459,10 @@ def test_lower_pulled_out_jump():
loop(simple_if('b', simple_if('c', [], continue_()),
lowered_return_simple()) +
break_()) +
- if_not_return_flag(assign_x('d', const_float(1))))
+
+ if_return_flag(assign_x('return_flag', const_bool(1)) +
+ assign_x('execute_flag', const_bool(0)),
+ assign_x('d', const_float(1))))
))
create_test_case(doc_string, input_sexp, expected_sexp,
'lower_pulled_out_jump',
lower_main_return=True, pull_out_jumps=True)
@@ -583,11 +593,14 @@ def test_lower_return_void_at_end_of_loop():
assign_x('b', const_float(2))
))
expected_sexp = make_test_case('main', 'void', (
+ declare_execute_flag() +
declare_return_flag() +
loop(assign_x('a', const_float(1)) +
lowered_return_simple() +
break_()) +
- if_not_return_flag(assign_x('b', const_float(2)))
+ if_return_flag(assign_x('return_flag', const_bool(1)) +
+ assign_x('execute_flag', const_bool(0)),
+ assign_x('b', const_float(2)))
))
create_test_case(doc_string, input_sexp, input_sexp,
'return_void_at_end_of_loop_lower_nothing')
create_test_case(doc_string, input_sexp, expected_sexp,
'return_void_at_end_of_loop_lower_return',
commit 2f86b7398a646dc95748cc314edb2ba0e3d25ef7
Author: Juan A. Suarez Romero <jasua...@igalia.com>
Date: Tue Mar 28 18:00:39 2017 +0200
tests/cache_test: allow crossing mount points
When using an overlayfs system (like a Docker container), rmrf_local()
fails because part of the files to be removed are in different mount
points (layouts). And thus cache-test fails.
Letting crossing mount points is not a big problem, specially because
this is just for a test, not to be used in real code.
Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com>
(cherry picked from commit caa616ccc4384ea1479865e12b56cf816561a827)
diff --git a/src/compiler/glsl/tests/cache_test.c
b/src/compiler/glsl/tests/cache_test.c
index 0ef05aa..efe4a9b 100644
--- a/src/compiler/glsl/tests/cache_test.c
+++ b/src/compiler/glsl/tests/cache_test.c
@@ -111,7 +111,7 @@ rmrf_local(const char *path)
if (path == NULL || *path == '\0' || *path != '.')
return -1;
- return nftw(path, remove_entry, 64, FTW_DEPTH | FTW_PHYS | FTW_MOUNT);
+ return nftw(path, remove_entry, 64, FTW_DEPTH | FTW_PHYS);
}
#define CACHE_TEST_TMP "./cache-test-tmp"
commit dc01cb9c5f38d6cdbb583ba70db5e51cc8901236
Author: Andres Gomez <ago...@igalia.com>
Date: Wed Feb 22 17:03:22 2017 +0200
glsl: on UBO/SSBOs link error reset the number of active blocks to 0
While it's legal to have an active blocks count > 0 on link failure.
Unless we actually assign memory for the blocks array we can end up
segfaulting in calls such as glUniformBlockBinding().
To avoid having to NULL check these api calls we simply reset the
block count to 0 if the array was not created.
Signed-off-by: Andres Gomez <ago...@igalia.com>
Cc: Timothy Arceri <tarc...@itsqueeze.com>
Reviewed-by: Timothy Arceri <tarc...@itsqueeze.com>
(cherry picked from commit bf15b2b515d5f37fc67fea77dea9d2fbc1dc8bf1)
diff --git a/src/compiler/glsl/linker.cpp b/src/compiler/glsl/linker.cpp
index d187b66..9f1d6b7 100644
--- a/src/compiler/glsl/linker.cpp
+++ b/src/compiler/glsl/linker.cpp
@@ -1176,6 +1176,12 @@ interstage_cross_validate_uniform_blocks(struct
gl_shader_program *prog,
for (unsigned k = 0; k <= i; k++) {
delete[] InterfaceBlockStageIndex[k];
}
+
+ /* Reset the block count. This will help avoid various segfaults
+ * from api calls that assume the array exists due to the count
+ * being non-zero.
+ */
+ *num_blks = 0;
return false;
}
commit fb00f22b835f76b88c996e479fc583e86e4d6006
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Tue Mar 14 17:52:12 2017 -0700
anv/query: Fix the location of timestamp availability
Reviewed-By: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Cc: "17.0 13.0" <mesa-...@lists.freedesktop.org>
(cherry picked from commit 4bbb4b95b8ba02693f5e6990b983ebb66dc6241a)
[Andres Gomez: use genX_cmd_buffer.c instead of genX_query.c]
Signed-off-by: Andres Gomez <ago...@igalia.com>
Conflicts:
src/intel/vulkan/genX_query.c
diff --git a/src/intel/vulkan/genX_cmd_buffer.c
b/src/intel/vulkan/genX_cmd_buffer.c
index e70ea7e..320b050 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -2577,7 +2577,7 @@ void genX(CmdWriteTimestamp)(
break;
}
- emit_query_availability(cmd_buffer, &pool->bo, query + 16);
+ emit_query_availability(cmd_buffer, &pool->bo, offset + 16);
}
#if GEN_GEN > 7 || GEN_IS_HASWELL
commit 45e133ab3bc0d182e5a2a8ebd4db725499c8ab09
Author: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl>
Date: Tue Mar 28 01:48:15 2017 +0200
radv: flush DB cache before and after HTILE decompress.
It reads @ writes the DB cache, and we haven't flushed dst caches yet,
so DB cache may be stale. Also the user might be shader read (and probably
is),
so also flush after.
Signed-off-by: Bas Nieuwenhuizen <ba...@google.com>
Reviewed-by: Dave Airlie <airl...@redhat.com>
CC: <mesa-sta...@lists.freedesktop.org>
Fixes: f4e499ec791 ("radv: add initial non-conformant radv vulkan driver")
(cherry picked from commit a8c51b1cd9168b621e27cf5308d0dd8fc08f8a4a)
[Andres Gomez: resolve trivial conflicts]
Signed-off-by: Andres Gomez <ago...@igalia.com>
Conflicts:
src/amd/vulkan/radv_cmd_buffer.c
