Timo Aaltonen pushed to branch ubuntu at X Strike Force / lib / mesa
Commits: 69ef6e4a by Juan A. Suarez Romero at 2018-05-17T18:40:11+00:00 docs: add sha256 checksums for 18.0.4 Signed-off-by: Juan A. Suarez Romero <[email protected]> - - - - - 309509bb by Dylan Baker at 2018-05-18T16:35:59-07:00 docs: Add sha sums for release - - - - - c3ac3fea by Dave Airlie at 2018-05-18T16:47:02-07:00 radv/resolve: do fmask decompress on all layers. For a multi-layer subpass resolve we want to make sure we flush all the layers. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Cc: <[email protected]> (cherry picked from commit b16fc6cda11576a4dd6c8d95f7bee94121c4b8e7) - - - - - 73b78286 by Dave Airlie at 2018-05-18T16:47:02-07:00 radv: resolve all layers in compute resolve path. This path should iterate across all layers, I've some ideas for doing this in a single pass, but this is simpler for now. This passes the tests because we don't use the fragment path unless we have DCC, and we don't have DCC on layered images. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Cc: <[email protected]> (cherry picked from commit 98dbaa445a83108b59bd56e8f3224c13c36ba1d5) - - - - - 0ea288d5 by Dave Airlie at 2018-05-18T16:47:02-07:00 radv: use compute path for multi-layer images. I don't think the hw resolve path can't handle multi-layer images. This fixes all the: dEQP-VK.renderpass.multisample_resolve.layers_* tests on my VI card. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Cc: <[email protected]> (cherry picked from commit 5978d54a09e6ad151c0bd365de0e2c82bbf493d1) - - - - - f8a82e13 by Bas Nieuwenhuizen at 2018-05-18T16:47:02-07:00 radv: Fix multiview queries. This moves the extra queries to after the main query ended, instead of doing it after the begin and hence doing nesting. We also emit only (view count - 1) extra queries, as the main query is already there for the first view. This fixes the CTS occasionally getting stuck in dEQP-VK.multiview.queries* waiting on results. Fixes: 32b4f3c38dc "radv/query: handle multiview queries properly. (v3)" CC: 18.1 <[email protected]> Reviewed-by: Dave Airlie <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> (cherry picked from commit 62f50df7b79c273a0eb9bf769eded76933bddc3a) - - - - - 15e7f80c by Bas Nieuwenhuizen at 2018-05-18T16:47:02-07:00 radv: Translate logic ops. radeonsi could pass them through but the enum changed between Gallium and Vulkan, so we have to translate. In progress I made the register defines a bit more readable. CC: 18.0 18.1 <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100430 Reviewed-by: Samuel Pitoiset <[email protected]> (cherry picked from commit dd102405dea022f6c27bc42176f50f3bb2761ae6) - - - - - 0d321533 by Bas Nieuwenhuizen at 2018-05-18T16:47:02-07:00 radv: Fix up 2_10_10_10 alpha sign. Pre-Vega HW always interprets the alpha for this format as unsigned, so we have to implement a fixup to do the sign correctly for signed formats. v2: Improve indexing mess. CC: 18.0 18.1 <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106480 Reviewed-by: Samuel Pitoiset <[email protected]> (cherry picked from commit 3d4d388e3929d7948b62d90867357aecbfba5aeb) - - - - - 287b2869 by Bas Nieuwenhuizen at 2018-05-18T16:47:02-07:00 radv: Disable texel buffers with A2 SNORM/SSCALED/SINT for pre-vega. The hardware always interprets the alpha as unsigned and fixing it in the shader is going to add unacceptable overheads. CC: 18.0 18.1 <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106480 Reviewed-by: Samuel Pitoiset <[email protected]> (cherry picked from commit f944a59996287de85d4c6d9b7b000d25f41b1d79) - - - - - 30e5b42f by Kai Wasserbäch at 2018-05-18T16:47:02-07:00 opencl: autotools: Fix linking order for OpenCL target Otherwise the build fails with an undefined reference to clang::FrontendTimesIsEnabled. Bugzilla: https://bugs.freedesktop.org/106209 Cc: Jan Vesely <[email protected]> Cc: [email protected] Signed-off-by: Kai Wasserbäch <[email protected]> Acked-by: Jan Vesely <[email protected]> Tested-by: Aaron Watry <[email protected]> Tested-by: Dieter Nützel <[email protected]> (cherry picked from commit b691d9192c436aba5a76577b7d772a791283a2e2) - - - - - 16591fee by Samuel Pitoiset at 2018-05-18T16:47:02-07:00 spirv: fix visiting inner loops with same break/continue block We should stop walking through the CFG when the inner loop's break block ends up as the same block as the outer loop's continue block because we are already going to visit it. This fixes the following assertion which ends up by crashing in RADV or ANV: SPIR-V parsing FAILED: In file ../src/compiler/spirv/vtn_cfg.c:381 block->node.link.next == NULL 0 bytes into the SPIR-V binary This also fixes a crash with a camera shader from SteamVR. v2: make use of vtn_get_branch_type() and add an assertion Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106090 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106504 CC: 18.0 18.1 <[email protected]> Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> (cherry picked from commit 6bde8c560877512852ff49fafa296eb71a5ec14b) - - - - - ac152cb1 by Jan Vesely at 2018-05-18T16:47:02-07:00 eg/compute: Use reference counting to handle compute memory pool. Use pipe_reference to release old RAT surfaces. RAT surface adds a reference to pool bo, so use reference counting for pool->bo as well. v2: Use the same pattern for both defrag paths Drop confusing comment CC: <[email protected]> Signed-off-by: Jan Vesely <[email protected]> Reviewed-by: Dave Airlie <[email protected]> (cherry picked from commit f3521ce2c440bd50020a3ff81e6d9fa17c01009c) - - - - - 0f7b29aa by Samuel Pitoiset at 2018-05-22T13:03:34+02:00 spirv: fix visiting inner loops with same break/continue block We should stop walking through the CFG when the inner loop's break block ends up as the same block as the outer loop's continue block because we are already going to visit it. This fixes the following assertion which ends up by crashing in RADV or ANV: SPIR-V parsing FAILED: In file ../src/compiler/spirv/vtn_cfg.c:381 block->node.link.next == NULL 0 bytes into the SPIR-V binary This also fixes a crash with a camera shader from SteamVR. v2: make use of vtn_get_branch_type() and add an assertion Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106090 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106504 CC: 18.0 18.1 <[email protected]> Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> (cherry picked from commit 6bde8c560877512852ff49fafa296eb71a5ec14b) - - - - - 712456cb by Jan Vesely at 2018-05-22T13:03:34+02:00 eg/compute: Use reference counting to handle compute memory pool. Use pipe_reference to release old RAT surfaces. RAT surface adds a reference to pool bo, so use reference counting for pool->bo as well. v2: Use the same pattern for both defrag paths Drop confusing comment CC: <[email protected]> Signed-off-by: Jan Vesely <[email protected]> Reviewed-by: Dave Airlie <[email protected]> (cherry picked from commit f3521ce2c440bd50020a3ff81e6d9fa17c01009c) - - - - - f084db88 by Stuart Young at 2018-05-22T13:03:34+02:00 etnaviv: Fix missing rnndb file in tarballs Seems that when the rnndb files for etniviv were updated/included back in Nov 2017, hw/texdesc_3d.xml.h was missed from Makefile.sources and meson.build. This was all during the conversion to meson, so it apears to have slipped through the cracks. As such, this file has been missing from the official tarballs since inclusion in Mesa, so the git trees and tarballs differ. Found due to lintian errors in the Debian packages. Fixes: f1e1c60ff6 ("etnaviv: Update from rnndb") Cc: [email protected] Reviewed-by: Christian Gmeiner <[email protected]> (cherry picked from commit f806cc9eb6be1a84a9987b142e7fce1ec2cb7973) - - - - - 544a3838 by Juan A. Suarez Romero at 2018-05-22T13:03:34+02:00 cherry-ignore: i965/miptree: Fix handling of uninitialized MCS buffers stable: The commit requires earlier commit af4e9295fe which did not land in branch. Signed-off-by: Juan A. Suarez Romero <[email protected]> - - - - - 3b7134c5 by Nanley Chery at 2018-05-22T13:03:34+02:00 i965/miptree: Zero-initialize CCS_D buffers Before this patch, the aux_state was actually AUX_INVALID because the BO was never defined. This was fine on single slice miptrees because we would fast-clear the resource right after creation. For multi-slice miptrees on SKL+ however, this results in undefined behavior when accessing a non-base slice. Here's a specific example: 1) Fast clear level 0 * Undefined CCS_D buffer allocated in "PASS_THROUGH" state. * Level 0 transitions to the CLEAR state. 2) Render to level 1 * Level 1 may have a 2-bit pattern of 2's. * Rendering with a 2 in the CCS is undefined. Cc: <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> (cherry picked from commit 8a9491058da72ee2df75da25bb147010a451fb68) [Juan A. Suarez: resolve trivial conflicts] Signed-off-by: Juan A. Suarez Romero <[email protected]> Conflicts: src/mesa/drivers/dri/i965/intel_mipmap_tree.c - - - - - 6ce8a775 by Bas Nieuwenhuizen at 2018-05-22T13:03:34+02:00 amd/addrlib: Use defines in autotools build. Otherwise stuff like NDEBUG would not be passed through. CC: <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106479 Reviewed-by: Marek Olšák <[email protected]> (cherry picked from commit 62e0e089d710835d9f79138377bcc37147f75ebd) - - - - - e7b50640 by Juan A. Suarez Romero at 2018-05-22T13:03:34+02:00 cherry-ignore: add explicit 18.1 only nominations Signed-off-by: Juan A. Suarez Romero <[email protected]> - - - - - 5cef37e9 by Bas Nieuwenhuizen at 2018-05-22T13:03:34+02:00 radv: Fix SRGB compute copies. SRGB stores are broken. We had compensation code in the resolve path but none in the copy path. Since we don't want any conversion and it does not matter for DCC, just make everything UNORM instead. This happened to cause wrong colors for the PRIME path, as that uses image->buffer copies which always use the compute path. CC: 18.0 18.1 <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106587 Reviewed-by: Dave Airlie <[email protected]> (cherry picked from commit a63a0960e3ebf049e593f51ce1e02dc84254f9c4) - - - - - 5443d858 by Juan A. Suarez Romero at 2018-05-22T13:03:34+02:00 cherry-ignore: mesa/st: handle vert_attrib_mask in nir case too fixes: The commit fixes earlier commits 19a91841c3 and 9987a072cb which did not land in branch. Signed-off-by: Juan A. Suarez Romero <[email protected]> - - - - - 620be4d4 by Timothy Arceri at 2018-05-22T13:03:34+02:00 mesa: add glUniform*ui{v} support to display lists Fixes: a017c7ecb7ae "mesa: display list support for uint uniforms" Reviewed-by: Marek Olšák <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78097 (cherry picked from commit f71714022b2cd26bb1892e6a7f3d7308515f210e) - - - - - f844591e by Anuj Phogat at 2018-05-22T13:03:34+02:00 i965/glk: Add l3 banks count for 2x6 configuration 2x6 configuration with pci-id 0x3185 has same number of banks (2) as 3x6 configuration (pci-id 0x3184). Reported-by: Clayton Craft <[email protected]> Signed-off-by: Anuj Phogat <[email protected]> Tested-by: Clayton Craft <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Fixes: eb23be1d97da "i965: Add and initialize l3_banks field for gen7+" Cc: Francisco Jerez <[email protected]> (cherry picked from commit 0748383a6014886ef0bf7bda16fd0efef39c405d) - - - - - 96b1ac39 by Samuel Pitoiset at 2018-05-22T13:03:34+02:00 radv: fix centroid interpolation It's legal to set the centroid and sample interpolation modes when MSAA disabled. So, we have to initialize the centroid inputs because the hardware doesn't. This fixes rendering issues with DXVK and The Witness, World of Warcraft, Trackmania and probably more games. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106315 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102390 CC: 18.0 18.1 <[email protected]> Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> (cherry picked from commit 73df16dcee79e2281c8d8a830dbbe6655359c82d) [Juan A. Suarez: apply change in src/amd/common/ac_nir_to_llvm.c] Signed-off-by: Juan A. Suarez Romero <[email protected]> Conflicts: src/amd/vulkan/radv_nir_to_llvm.c - - - - - b582b8fc by Michel Dänzer at 2018-05-23T16:28:02+02:00 dri3: Stricter SBC wraparound handling Prevents corrupting the upper 32 bits of draw->recv_sbc when draw->send_sbc resets to 0 (which currently happens when the window is unbound from a context and bound to one again), which in turn caused loader_dri3_swap_buffers_msc to calculate target_msc with corrupted upper 32 bits. This resulted in hangs with the Xorg modesetting driver as of xserver 1.20 (older versions and other drivers ignored the upper 32 bits of the target MSC, which is why this wasn't noticed earlier). Cc: [email protected] Bugzilla: https://bugs.freedesktop.org/106351 Tested-by: Mike Lothian <[email protected]> (cherry picked from commit fe2edb25dd5628c395a65b60998f11e839d2b458) [Juan A. Suarez: resolve trivial conflicts] Conflicts: src/loader/loader_dri3_helper.c - - - - - 6a0c2860 by Dave Airlie at 2018-05-23T16:28:02+02:00 tgsi/scan: add hw atomic to the list of memory accessing files This fixes 4 out of 5 cases in: arb_framebuffer_no_attachments-atomic on cayman. Reviewed-by: Marek Olšák <[email protected]> Cc: "18.0 18.1" <[email protected]> (cherry picked from commit f2f464de576187891eeadb3e7fadf9ddbf322cba) - - - - - a93a86a4 by Jason Ekstrand at 2018-05-23T16:28:02+02:00 intel/eu: Set EXECUTE_1 when setting the rounding mode in cr0 Fixes: d6cd14f2131a5b "i965/fs: Define new shader opcode to..." Reviewed-by: Jose Maria Casanova Crespo <[email protected]> (cherry picked from commit 417b9e5770436008a7f00cfaffe9ddf4c5a13502) - - - - - 8d5f09e8 by Francisco Jerez at 2018-05-24T10:35:26+00:00 Revert "mesa: simplify _mesa_is_image_unit_valid for buffers" This reverts commit c0ed52f6146c7e24e1275451773bd47c1eda3145. It was preventing the image format validation from being done on buffer textures, which is required to ensure that the application doesn't attempt to bind a buffer texture with an internal format incompatible with the image unit format (e.g. of different texel size), which is not allowed by the spec (it's not allowed for *any* texture target, whether or not there is spec wording restricting this behavior specifically for buffer textures) and will cause the driver to calculate texel bounds incorrectly and potentially crash instead of the expected behavior. Cc: [email protected] Reviewed-by: Marek Olšák <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106465 Reviewed-by: Nanley Chery <[email protected]> (cherry picked from commit 5a6814780322988a7adee525899bca8a83907ab7) - - - - - 03eaee15 by Francisco Jerez at 2018-05-24T10:35:26+00:00 i965: Move buffer texture size calculation into a common helper function. The buffer texture size calculations (should be easy enough, right?) are repeated in three different places, each of them subtly broken in a different way. E.g. the image load/store path was never fixed to clamp to MaxTextureBufferSize, and none of them are taking into account the buffer offset correctly. It's easier to fix it all in one place. Cc: [email protected] Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106481 Reviewed-by: Nanley Chery <[email protected]> (cherry picked from commit 156d2c6e621d836c4d45c636b87669e1de3d4464) - - - - - 86e749a9 by Francisco Jerez at 2018-05-24T10:35:26+00:00 i965: Handle non-zero texture buffer offsets in buffer object range calculation. Otherwise the specified surface state will allow the GPU to access memory up to BufferOffset bytes past the end of the buffer. Found by inspection. v2: Protect against out-of-range BufferOffset (Nanley). Cc: [email protected] Reviewed-by: Nanley Chery <[email protected]> (cherry picked from commit e989acb03ba802737f762627dd16ac1d0b9f0d13) - - - - - 42fa7cf2 by Francisco Jerez at 2018-05-24T10:35:26+00:00 i965: Use intel_bufferobj_buffer() wrapper in image surface state setup. Instead of directly using intel_obj->buffer. Among other things intel_bufferobj_buffer() will update intel_buffer_object:: gpu_active_start/end, which are used by glBufferSubData() to decide which path to take. Fixes a failure in the Piglit ARB_shader_image_load_store-host-mem-barrier Buffer Update/WaW tests, which could be reproduced with a non-standard glGetTexSubImage implementation (see bug report). Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105351 Reported-by: Nanley Chery <[email protected]> Cc: [email protected] Reviewed-by: Nanley Chery <[email protected]> (cherry picked from commit 936cd3c87a212c28fe89a5c059fc4febd8b52ab7) - - - - - 1939affe by Jose Dapena Paz at 2018-05-25T09:59:18+02:00 mesa: do not leak ctx->Shader.ReferencedProgram references When glUseProgram is used, references to the included shaders are added in ctx->Shader.ReferencedProgram. But those references are not decreased when the shader data is deallocated. Thus, those shaders are leaked. Explicitely remove the pending references to these shaders. Fixes: e6506b3cd23 ("mesa: retain gl_shader_programs after glDeleteProgram if they are in use") Reviewed-by: Timothy Arceri <[email protected]> (cherry picked from commit 6c61c31dc2fe52ad8a56ebe0b3aa10c223b635ba) - - - - - 8cf02769 by Marek Olšák at 2018-05-28T10:39:48+02:00 st/mesa: simplify lastLevel determination in st_finalize_texture This fixes shader images where we always bind stObj->pt and not individual gl_texture_images. Roughly based on i965 commit 845ad2667ab2466752f06ea30bdb9c837116c308 which does a similar thing but for a different reason. This fixes GL CTS assertion failures introduced by Ilia. Cc: 18.0 18.1 <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]> (cherry picked from commit a4ba7cd6a2fc2718c3b4f9107d676ad1bfd02bf1) - - - - - 38aeeee5 by Marek Olšák at 2018-05-28T10:39:48+02:00 radeonsi: fix incorrect parentheses around VS-PS varying elimination I don't know if it caused issues. Cc: 18.0 18.1 <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]> (cherry picked from commit 92ea9329e5eacf9a44ed30b3d72038a411eb771a) - - - - - aac580f7 by Jason Ekstrand at 2018-05-28T10:39:48+02:00 intel/blorp: Support blits and clears on surfaces with offsets For certain EGLImage cases, we represent a single slice or LOD of an image with a byte offset to a tile and X/Y intratile offsets to the given slice. Most of i965 is fine with this but it breaks blorp. This is a terrible way to represent slices of a surface in EGL and we should stop some day but that's a very scary and thorny path. This gets blorp to start working with those surfaces and fixes some dEQP EGL test bugs. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106629 Cc: [email protected] Reviewed-by: Kenneth Graunke <[email protected]> (cherry picked from commit ae514ca695a599cdd0b7c22f48fd4d721671b0cb) - - - - - 714dabe3 by Juan A. Suarez Romero at 2018-05-30T10:06:43+02:00 cherry-ignore: Tegra is not supported stable: Tegra support was not added in the current branch. Signed-off-by: Juan A. Suarez Romero <[email protected]> - - - - - 81bd117b by Marek Olšák at 2018-05-30T10:06:43+02:00 mesa: handle GL_UNSIGNED_INT64_ARB properly (v2) Bindless texture handles can be passed via vertex attribs using this type. This fixes a bunch of bindless piglit tests on radeonsi. Cc: 18.0 18.1 <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]> (cherry picked from commit a8e141387686cdf44b5868031283267acb99eba7) [Juan A. Suarez: resolve trivial conflict] Signed-off-by: Juan A. Suarez Romero <[email protected]> Conflicts: src/mesa/vbo/vbo_private.h - - - - - dfa3a7ee by Juan A. Suarez Romero at 2018-05-30T10:06:43+02:00 cherry-ignore: st/mesa: fix assertion failures with GL_UNSIGNED_INT64_ARB (v2) stable: The commit requires earlier commit 19a91841c3 which did not land in branch. Signed-off-by: Juan A. Suarez Romero <[email protected]> - - - - - 7c644f48 by Juan A. Suarez Romero at 2018-05-30T10:06:43+02:00 cherry-ignore: nv30: ensure that displayable formats are marked accordingly stable: Explicit 18.1 only nomination. Signed-off-by: Juan A. Suarez Romero <[email protected]> - - - - - 4978181f by Stuart Young at 2018-05-30T16:56:47-07:00 etnaviv: Fix missing rnndb file in tarballs Seems that when the rnndb files for etniviv were updated/included back in Nov 2017, hw/texdesc_3d.xml.h was missed from Makefile.sources and meson.build. This was all during the conversion to meson, so it apears to have slipped through the cracks. As such, this file has been missing from the official tarballs since inclusion in Mesa, so the git trees and tarballs differ. Found due to lintian errors in the Debian packages. Fixes: f1e1c60ff6 ("etnaviv: Update from rnndb") Cc: [email protected] Reviewed-by: Christian Gmeiner <[email protected]> (cherry picked from commit f806cc9eb6be1a84a9987b142e7fce1ec2cb7973) - - - - - c9074b3c by Timothy Arceri at 2018-05-30T16:56:47-07:00 mesa: add glUniform*ui{v} support to display lists Fixes: a017c7ecb7ae "mesa: display list support for uint uniforms" Reviewed-by: Marek Olšák <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78097 (cherry picked from commit f71714022b2cd26bb1892e6a7f3d7308515f210e) - - - - - db4e3450 by Nanley Chery at 2018-05-30T16:56:47-07:00 i965: Add and use a getter for the miptree aux buffer Make the next patch easier to read by eliminating most of the would-be duplicate field accesses now. v2: Update the HiZ comment instead of deleting it (Rafael). Reviewed-by: Rafael Antognolli <[email protected]> (cherry picked from commit 5503b65103b6a93dabe609cbedbbc999dd63bff5) - - - - - 21d51b4c by Nanley Chery at 2018-05-30T16:56:47-07:00 i965: Add and use a single miptree aux_buf field We want to add and use a function that accesses the auxiliary buffer's clear_color_bo and doesn't care if it has an MCS or HiZ buffer specifically. v2 (Jason Ekstrand): * Drop intel_miptree_get_aux_buffer(). * Mention CCS in the aux_buf field. Reviewed-by: Rafael Antognolli <[email protected]> (v1) Reviewed-by: Jason Ekstrand <[email protected]> (cherry picked from commit af4e9295febe966ace7793e43ba35705521749e8) - - - - - 66fa6ece by Nanley Chery at 2018-05-30T16:56:47-07:00 i965/miptree: Fix handling of uninitialized MCS buffers Before this patch, if we failed to initialize an MCS buffer, we'd end up in a state in which the miptree thinks it has an MCS buffer, but doesn't. We also leaked the clear_color_bo if it existed. With this patch, we now free the miptree aux buffer resources and let intel_miptree_alloc_mcs() know that the MCS buffer no longer exists. Cc: <[email protected]> Reviewed-by: Tapani Pälli <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> (cherry picked from commit 816f2dc67da72be8993e724aeda4c2ec2f5a2978) - - - - - 6fe826ee by Nanley Chery at 2018-05-30T16:56:47-07:00 i965/miptree: Zero-initialize CCS_D buffers Before this patch, the aux_state was actually AUX_INVALID because the BO was never defined. This was fine on single slice miptrees because we would fast-clear the resource right after creation. For multi-slice miptrees on SKL+ however, this results in undefined behavior when accessing a non-base slice. Here's a specific example: 1) Fast clear level 0 * Undefined CCS_D buffer allocated in "PASS_THROUGH" state. * Level 0 transitions to the CLEAR state. 2) Render to level 1 * Level 1 may have a 2-bit pattern of 2's. * Rendering with a 2 in the CCS is undefined. Cc: <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> (cherry picked from commit 8a9491058da72ee2df75da25bb147010a451fb68) - - - - - 5b79bbe2 by Christoph Haag at 2018-05-30T16:56:47-07:00 radv: fix VK_EXT_descriptor_indexing GetPhysicalDeviceProperties2KHR() was crashing because features was null Fixes: 0e10790558b "radv: Enable VK_EXT_descriptor_indexing." CC: 18.1 <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> (cherry picked from commit 549e54270ba3a519b46a1fbffa4aa6b628a052d3) - - - - - 5d4b5b07 by Dave Airlie at 2018-05-30T16:56:47-07:00 virgl: set texture buffer offset alignment to disable ARB_texture_buffer_range. The host side hasn't got support for this feature yet, so don't enable it unless we get the caps from the host. This makes the texture buffer range piglit tests skip now. Fixes: fe0647df5a7 (virgl: add offset alignment values to to v2 caps struct) Reviewed-by: Gurchetan Singh <[email protected]> (cherry picked from commit bfa74bb44ddf3e81dedf9af28f86110dfd47dc45) - - - - - f969afdf by Bas Nieuwenhuizen at 2018-05-30T16:56:47-07:00 amd/addrlib: Use defines in autotools build. Otherwise stuff like NDEBUG would not be passed through. CC: <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106479 Reviewed-by: Marek Olšák <[email protected]> (cherry picked from commit 62e0e089d710835d9f79138377bcc37147f75ebd) - - - - - b49daeac by Bas Nieuwenhuizen at 2018-05-30T16:56:47-07:00 radv: Fix SRGB compute copies. SRGB stores are broken. We had compensation code in the resolve path but none in the copy path. Since we don't want any conversion and it does not matter for DCC, just make everything UNORM instead. This happened to cause wrong colors for the PRIME path, as that uses image->buffer copies which always use the compute path. CC: 18.0 18.1 <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106587 Reviewed-by: Dave Airlie <[email protected]> (cherry picked from commit a63a0960e3ebf049e593f51ce1e02dc84254f9c4) - - - - - fd18f81a by Samuel Pitoiset at 2018-05-30T16:56:47-07:00 radv: fix centroid interpolation It's legal to set the centroid and sample interpolation modes when MSAA disabled. So, we have to initialize the centroid inputs because the hardware doesn't. This fixes rendering issues with DXVK and The Witness, World of Warcraft, Trackmania and probably more games. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106315 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102390 CC: 18.0 18.1 <[email protected]> Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> (cherry picked from commit 73df16dcee79e2281c8d8a830dbbe6655359c82d) - - - - - 66604a75 by Anuj Phogat at 2018-05-30T16:56:47-07:00 i965/glk: Add l3 banks count for 2x6 configuration 2x6 configuration with pci-id 0x3185 has same number of banks (2) as 3x6 configuration (pci-id 0x3184). Reported-by: Clayton Craft <[email protected]> Signed-off-by: Anuj Phogat <[email protected]> Tested-by: Clayton Craft <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Fixes: eb23be1d97da "i965: Add and initialize l3_banks field for gen7+" Cc: Francisco Jerez <[email protected]> (cherry picked from commit 0748383a6014886ef0bf7bda16fd0efef39c405d) - - - - - 14689dcc by Jason Ekstrand at 2018-05-30T16:56:47-07:00 intel/eu: Set EXECUTE_1 when setting the rounding mode in cr0 Fixes: d6cd14f2131a5b "i965/fs: Define new shader opcode to..." Reviewed-by: Jose Maria Casanova Crespo <[email protected]> (cherry picked from commit 417b9e5770436008a7f00cfaffe9ddf4c5a13502) - - - - - e4b86e96 by Michel Dänzer at 2018-05-30T16:56:47-07:00 dri3: Stricter SBC wraparound handling Prevents corrupting the upper 32 bits of draw->recv_sbc when draw->send_sbc resets to 0 (which currently happens when the window is unbound from a context and bound to one again), which in turn caused loader_dri3_swap_buffers_msc to calculate target_msc with corrupted upper 32 bits. This resulted in hangs with the Xorg modesetting driver as of xserver 1.20 (older versions and other drivers ignored the upper 32 bits of the target MSC, which is why this wasn't noticed earlier). Cc: [email protected] Bugzilla: https://bugs.freedesktop.org/106351 Tested-by: Mike Lothian <[email protected]> (cherry picked from commit fe2edb25dd5628c395a65b60998f11e839d2b458) - - - - - 7366a913 by Dave Airlie at 2018-05-30T16:56:47-07:00 tgsi/scan: add hw atomic to the list of memory accessing files This fixes 4 out of 5 cases in: arb_framebuffer_no_attachments-atomic on cayman. Reviewed-by: Marek Olšák <[email protected]> Cc: "18.0 18.1" <[email protected]> (cherry picked from commit f2f464de576187891eeadb3e7fadf9ddbf322cba) - - - - - d795a1a6 by Francisco Jerez at 2018-05-30T16:56:47-07:00 Revert "mesa: simplify _mesa_is_image_unit_valid for buffers" This reverts commit c0ed52f6146c7e24e1275451773bd47c1eda3145. It was preventing the image format validation from being done on buffer textures, which is required to ensure that the application doesn't attempt to bind a buffer texture with an internal format incompatible with the image unit format (e.g. of different texel size), which is not allowed by the spec (it's not allowed for *any* texture target, whether or not there is spec wording restricting this behavior specifically for buffer textures) and will cause the driver to calculate texel bounds incorrectly and potentially crash instead of the expected behavior. Cc: [email protected] Reviewed-by: Marek Olšák <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106465 Reviewed-by: Nanley Chery <[email protected]> (cherry picked from commit 5a6814780322988a7adee525899bca8a83907ab7) - - - - - 1b5f4fca by Francisco Jerez at 2018-05-30T16:56:47-07:00 i965: Move buffer texture size calculation into a common helper function. The buffer texture size calculations (should be easy enough, right?) are repeated in three different places, each of them subtly broken in a different way. E.g. the image load/store path was never fixed to clamp to MaxTextureBufferSize, and none of them are taking into account the buffer offset correctly. It's easier to fix it all in one place. Cc: [email protected] Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106481 Reviewed-by: Nanley Chery <[email protected]> (cherry picked from commit 156d2c6e621d836c4d45c636b87669e1de3d4464) - - - - - 9c1ab960 by Francisco Jerez at 2018-05-30T16:56:47-07:00 i965: Handle non-zero texture buffer offsets in buffer object range calculation. Otherwise the specified surface state will allow the GPU to access memory up to BufferOffset bytes past the end of the buffer. Found by inspection. v2: Protect against out-of-range BufferOffset (Nanley). Cc: [email protected] Reviewed-by: Nanley Chery <[email protected]> (cherry picked from commit e989acb03ba802737f762627dd16ac1d0b9f0d13) - - - - - 54ff5005 by Francisco Jerez at 2018-05-30T16:56:47-07:00 i965: Use intel_bufferobj_buffer() wrapper in image surface state setup. Instead of directly using intel_obj->buffer. Among other things intel_bufferobj_buffer() will update intel_buffer_object:: gpu_active_start/end, which are used by glBufferSubData() to decide which path to take. Fixes a failure in the Piglit ARB_shader_image_load_store-host-mem-barrier Buffer Update/WaW tests, which could be reproduced with a non-standard glGetTexSubImage implementation (see bug report). Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105351 Reported-by: Nanley Chery <[email protected]> Cc: [email protected] Reviewed-by: Nanley Chery <[email protected]> (cherry picked from commit 936cd3c87a212c28fe89a5c059fc4febd8b52ab7) - - - - - 7b588bf3 by Jose Dapena Paz at 2018-05-30T16:56:47-07:00 mesa: do not leak ctx->Shader.ReferencedProgram references When glUseProgram is used, references to the included shaders are added in ctx->Shader.ReferencedProgram. But those references are not decreased when the shader data is deallocated. Thus, those shaders are leaked. Explicitely remove the pending references to these shaders. Fixes: e6506b3cd23 ("mesa: retain gl_shader_programs after glDeleteProgram if they are in use") Reviewed-by: Timothy Arceri <[email protected]> (cherry picked from commit 6c61c31dc2fe52ad8a56ebe0b3aa10c223b635ba) - - - - - 3cb16ce7 by Marek Olšák at 2018-05-30T16:56:47-07:00 st/mesa: simplify lastLevel determination in st_finalize_texture This fixes shader images where we always bind stObj->pt and not individual gl_texture_images. Roughly based on i965 commit 845ad2667ab2466752f06ea30bdb9c837116c308 which does a similar thing but for a different reason. This fixes GL CTS assertion failures introduced by Ilia. Cc: 18.0 18.1 <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]> (cherry picked from commit a4ba7cd6a2fc2718c3b4f9107d676ad1bfd02bf1) - - - - - 36e65cc4 by Marek Olšák at 2018-05-30T16:56:47-07:00 radeonsi: fix incorrect parentheses around VS-PS varying elimination I don't know if it caused issues. Cc: 18.0 18.1 <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]> (cherry picked from commit 92ea9329e5eacf9a44ed30b3d72038a411eb771a) - - - - - 1dd9532d by Jason Ekstrand at 2018-05-30T16:56:47-07:00 intel/blorp: Support blits and clears on surfaces with offsets For certain EGLImage cases, we represent a single slice or LOD of an image with a byte offset to a tile and X/Y intratile offsets to the given slice. Most of i965 is fine with this but it breaks blorp. This is a terrible way to represent slices of a surface in EGL and we should stop some day but that's a very scary and thorny path. This gets blorp to start working with those surfaces and fixes some dEQP EGL test bugs. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106629 Cc: [email protected] Reviewed-by: Kenneth Graunke <[email protected]> (cherry picked from commit ae514ca695a599cdd0b7c22f48fd4d721671b0cb) - - - - - 2b8f87ce by Thierry Reding at 2018-05-30T16:56:47-07:00 tegra: Treat resources with modifiers as scanout Resources created with modifiers are treated as scanout because there is no way for applications to specify the usage (though that capability may be useful to have in the future). Currently all the resources created by applications with modifiers are for scanout, so make sure they have bind flags set accordingly. This is necessary in order to properly export buffers for such resources so that they can be shared with scanout hardware. Tested-by: Daniel Kolesa <[email protected]> Cc: [email protected] Signed-off-by: Thierry Reding <[email protected]> (cherry picked from commit 9e539012dfaa848fc4cfde83c3f3a83fee274ca4) - - - - - 92c63388 by Thierry Reding at 2018-05-30T16:56:47-07:00 tegra: Fix scanout resources without modifiers Resources created for scanout but without modifiers need to be treated as pitch-linear. This is because applications that don't use modifiers to create resources must be assumed to not understand modifiers and in turn won't be able to create a DRM framebuffer and passing along which modifiers were picked by the implementation. Tested-by: Daniel Kolesa <[email protected]> Cc: [email protected] Signed-off-by: Thierry Reding <[email protected]> (cherry picked from commit 9603d81df05105857b676f20dff964ef3ab0ecff) - - - - - 5015436e by Thierry Reding at 2018-05-30T16:56:47-07:00 tegra: Remove usage of non-stable UAPI This code path is no longer required with framebuffer modifier support. Tested-by: Daniel Kolesa <[email protected]> Cc: [email protected] Signed-off-by: Thierry Reding <[email protected]> (cherry picked from commit bd3e97e5aad7800b8e17ed10d34a070926691945) - - - - - 55de9df5 by Bas Nieuwenhuizen at 2018-05-30T16:56:47-07:00 radv: Only expose subgroup shuffles on VI+. The current implementation depends on bpermute, which is VI+. Fixes: f2c6a550611 "radv: enable subgroup capabilities" Reviewed-by: Daniel Schürmann <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> (cherry picked from commit c2799574eb104218ac4f6b8a3d64b8a0f8c89525) - - - - - b6167e96 by Ilia Mirkin at 2018-05-30T16:56:47-07:00 nv30: ensure that displayable formats are marked accordingly Fixes: f7604d8af52 ("st/dri: only expose config formats that are display targets") Cc: "18.1" <[email protected]> Signed-off-by: Ilia Mirkin <[email protected]> (cherry picked from commit 30918b77ac82ba1da7764c0375233656e0ebf9f9) - - - - - df303adc by Eric Engestrom at 2018-05-30T16:56:47-07:00 vulkan: don't free uninitialised memory The modifiers array hasn't been initialised by then, much less with data that would need freeing. Move the label after the loop to fix this. Fixes: c80c08e22603 ("vulkan/wsi/x11: Add support for DRI3 v1.2") Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> (cherry picked from commit e4fe2fd3bb26d52e64d98207692a4469f04fe1d5) - - - - - e3897b66 by Marek Olšák at 2018-05-30T16:56:47-07:00 mesa: handle GL_UNSIGNED_INT64_ARB properly (v2) Bindless texture handles can be passed via vertex attribs using this type. This fixes a bunch of bindless piglit tests on radeonsi. Cc: 18.0 18.1 <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]> (cherry picked from commit a8e141387686cdf44b5868031283267acb99eba7) - - - - - 32dbb286 by Dylan Baker at 2018-05-31T13:08:36-07:00 VERSION: bump to 18.1.1 for next release - - - - - 1f3536b8 by Dylan Baker at 2018-05-31T15:22:49-07:00 docs: Add release notes for 18.1.1 - - - - - 3f4da760 by Juan A. Suarez Romero at 2018-06-03T09:20:57+00:00 Update version to 18.0.5 Signed-off-by: Juan A. Suarez Romero <[email protected]> - - - - - ca0037aa by Juan A. Suarez Romero at 2018-06-03T09:26:20+00:00 docs: add release notes for 18.0.5 Signed-off-by: Juan A. Suarez Romero <[email protected]> - - - - - a52e5b98 by Emilio Pozuelo Monfort at 2018-06-03T19:25:40+02:00 Merge branch 'upstream-unstable' into debian-unstable - - - - - 8f6feea4 by Emilio Pozuelo Monfort at 2018-06-03T19:31:15+02:00 New upstream release - - - - - 311fae79 by Emilio Pozuelo Monfort at 2018-06-04T09:53:07+02:00 Release to unstable - - - - - 743ec528 by Timo Aaltonen at 2018-06-13T10:34:48+03:00 Merge tag 'mesa-18.0.5' into debian-experimental mesa-18.0.5 - - - - - e0c73c62 by Timo Aaltonen at 2018-06-13T10:34:56+03:00 Merge branch 'debian-unstable' into debian-experimental - - - - - 36cb990f by Timo Aaltonen at 2018-06-13T10:35:12+03:00 Merge branch 'upstream-unstable' into debian-experimental - - - - - 646ff326 by Timo Aaltonen at 2018-06-13T10:38:05+03:00 update the changelog - - - - - ddebefe8 by Timo Aaltonen at 2018-06-13T11:46:21+03:00 release to unstable - - - - - 10d46dac by Timo Aaltonen at 2018-06-13T12:04:18+03:00 Merge branch 'debian-unstable' into ubuntu - - - - - b04d4a41 by Timo Aaltonen at 2018-06-13T12:05:14+03:00 update the changelog - - - - - 3ae5309f by Timo Aaltonen at 2018-06-13T12:10:12+03:00 glvnd-fix-a-segfault-in-eglgetprocaddess.diff: Backport a commit to fix a segfault. (LP: #1776499) - - - - - d532f023 by Timo Aaltonen at 2018-06-13T12:10:43+03:00 release to cosmic - - - - - 30 changed files: - VERSION - debian/changelog - + debian/patches/glvnd-fix-a-segfault-in-eglgetprocaddess.diff - debian/patches/series - docs/relnotes/18.1.0.html - + docs/relnotes/18.1.1.html - src/amd/Makefile.addrlib.am - src/amd/common/sid.h - src/amd/vulkan/radv_device.c - src/amd/vulkan/radv_formats.c - src/amd/vulkan/radv_meta_copy.c - src/amd/vulkan/radv_meta_resolve.c - src/amd/vulkan/radv_meta_resolve_cs.c - src/amd/vulkan/radv_nir_to_llvm.c - src/amd/vulkan/radv_pipeline.c - src/amd/vulkan/radv_private.h - src/amd/vulkan/radv_query.c - src/amd/vulkan/radv_shader.h - src/amd/vulkan/vk_format.h - src/compiler/spirv/vtn_cfg.c - src/gallium/auxiliary/tgsi/tgsi_scan.c - src/gallium/drivers/etnaviv/Makefile.sources - src/gallium/drivers/etnaviv/meson.build - src/gallium/drivers/nouveau/nv30/nv30_format.c - src/gallium/drivers/r600/compute_memory_pool.c - src/gallium/drivers/r600/evergreen_compute.c - src/gallium/drivers/radeonsi/si_state_shaders.c - src/gallium/drivers/tegra/tegra_screen.c - src/gallium/drivers/virgl/virgl_winsys.h - src/gallium/targets/opencl/Makefile.am The diff was not included because it is too large. View it on GitLab: https://salsa.debian.org/xorg-team/lib/mesa/compare/b8edc04ca603f293fd9d7324897e1ec3315f2413...d532f023a4bee91a67de8a9963a0497e09dcf0e4 -- View it on GitLab: https://salsa.debian.org/xorg-team/lib/mesa/compare/b8edc04ca603f293fd9d7324897e1ec3315f2413...d532f023a4bee91a67de8a9963a0497e09dcf0e4 You're receiving this email because of your account on salsa.debian.org.
