.cvsignore | 20
.gitignore | 21
ChangeLog | 48 +
Makefile.in | 31
aclocal.m4 | 265 +++++--
config.guess | 60 +
config.h.in | 6
config.sub | 66 +
configure | 1256 +++++++++++++++++++++++++++++++------
configure.ac | 16
debian/changelog | 16
debian/control | 10
debian/patches/01_gen_pci_ids.diff | 18
debian/rules | 2
debian/xsfbs/xsfbs-autoreconf.mk | 150 ----
debian/xsfbs/xsfbs.mk | 121 ---
debian/xsfbs/xsfbs.sh | 394 ++++++-----
depcomp | 93 ++
install-sh | 514 ++++++++++-----
ltmain.sh | 277 +++++---
man/Makefile.am | 1
man/Makefile.in | 9
missing | 61 +
mkinstalldirs | 5
src/Makefile.am | 3
src/Makefile.in | 34 -
src/tseng.h | 12
src/tseng_accel.c | 1
src/tseng_acl.c | 232 ------
src/tseng_acl.h | 232 ------
src/tseng_bank.c | 87 --
src/tseng_clock.c | 509 --------------
src/tseng_colexp.c | 543 ---------------
src/tseng_cursor.c | 1
src/tseng_dga.c | 1
src/tseng_dpms.c | 248 -------
src/tseng_driver.c | 43 +
src/tseng_inline.h | 228 ------
src/tseng_pcirename.h | 122 +++
src/tseng_ramdac.c | 667 -------------------
40 files changed, 2544 insertions(+), 3879 deletions(-)
New commits:
commit b1b629df4b8aa009cb7109cf6e636ae84b5314ec
Author: Julien Cristau <[EMAIL PROTECTED]>
Date: Fri Jun 6 15:13:26 2008 +0200
Prepare changelog for upload
diff --git a/debian/changelog b/debian/changelog
index a0d3cfb..368d97d 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,4 +1,4 @@
-xserver-xorg-video-tseng (1:1.2.0-1) UNRELEASED; urgency=low
+xserver-xorg-video-tseng (1:1.2.0-1) unstable; urgency=low
[ Brice Goglin ]
* Add upstream URL to debian/copyright.
@@ -14,7 +14,7 @@ xserver-xorg-video-tseng (1:1.2.0-1) UNRELEASED; urgency=low
dpkg-shlibdeps to shut up about symbols it can't find. Build-depend on
dpkg-dev >= 1.14.17.
- -- Brice Goglin <[EMAIL PROTECTED]> Sat, 15 Sep 2007 02:25:46 +0200
+ -- Julien Cristau <[EMAIL PROTECTED]> Fri, 06 Jun 2008 15:13:21 +0200
xserver-xorg-video-tseng (1:1.1.1-4) unstable; urgency=low
commit 920e6ef85698736937f95062521d6587c1a3abec
Author: Julien Cristau <[EMAIL PROTECTED]>
Date: Fri Jun 6 15:13:17 2008 +0200
Run dpkg-shlibdeps with --warnings=6.
Drivers reference symbols from /usr/bin/Xorg and other modules,
and that's not a bug, so we want dpkg-shlibdeps to shut up about
symbols it can't find. Build-depend on dpkg-dev >= 1.14.17.
diff --git a/debian/changelog b/debian/changelog
index 7c7c0cf..a0d3cfb 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -9,6 +9,10 @@ xserver-xorg-video-tseng (1:1.2.0-1) UNRELEASED; urgency=low
* Remove Branden from Uploaders with his permission and add myself.
* Bump Standards-Version to 3.7.3.
* Drop the XS- prefix from Vcs-* control fields.
+ * Run dpkg-shlibdeps with --warnings=6. Drivers reference symbols from
+ /usr/bin/Xorg and other modules, and that's not a bug, so we want
+ dpkg-shlibdeps to shut up about symbols it can't find. Build-depend on
+ dpkg-dev >= 1.14.17.
-- Brice Goglin <[EMAIL PROTECTED]> Sat, 15 Sep 2007 02:25:46 +0200
diff --git a/debian/control b/debian/control
index 947be7c..c25caf8 100644
--- a/debian/control
+++ b/debian/control
@@ -3,7 +3,7 @@ Section: x11
Priority: optional
Maintainer: Debian X Strike Force <debian-x@lists.debian.org>
Uploaders: David Nusinow <[EMAIL PROTECTED]>, Julien Cristau <[EMAIL
PROTECTED]>
-Build-Depends: debhelper (>= 5.0.0), pkg-config, quilt, xserver-xorg-dev (>=
2:1.4), x11proto-video-dev, x11proto-core-dev, x11proto-fonts-dev,
x11proto-randr-dev, x11proto-render-dev, x11proto-xext-dev
+Build-Depends: debhelper (>= 5.0.0), pkg-config, quilt, xserver-xorg-dev (>=
2:1.4), x11proto-video-dev, x11proto-core-dev, x11proto-fonts-dev,
x11proto-randr-dev, x11proto-render-dev, x11proto-xext-dev, dpkg-dev (>=
1.14.17)
Standards-Version: 3.7.3
Vcs-Git: git://git.debian.org/git/pkg-xorg/driver/xserver-xorg-video-tseng
Vcs-Browser:
http://git.debian.org/?p=pkg-xorg/driver/xserver-xorg-video-tseng.git
diff --git a/debian/rules b/debian/rules
index 65f5b88..40968c7 100755
--- a/debian/rules
+++ b/debian/rules
@@ -78,7 +78,7 @@ binary-arch: build install serverabi
dh_compress
dh_fixperms
dh_installdeb
- dh_shlibdeps
+ dh_shlibdeps -- --warnings=6
dh_gencontrol
dh_md5sums
dh_builddeb
commit d58a3be4f281d6d80229d480374921c56fb42fe4
Author: Julien Cristau <[EMAIL PROTECTED]>
Date: Fri Jun 6 15:11:33 2008 +0200
Remove leftover files, they've been removed upstream long ago
diff --git a/src/tseng_acl.c b/src/tseng_acl.c
deleted file mode 100644
index b611ba7..0000000
--- a/src/tseng_acl.c
+++ /dev/null
@@ -1,232 +0,0 @@
-
-/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/tseng/tseng_acl.c,v 1.23
2000/08/08 08:58:06 eich Exp $ */
-
-#ifdef HAVE_CONFIG_H
-#include "config.h"
-#endif
-
-#include "tseng.h"
-#include "tseng_acl.h"
-#include "compiler.h"
-
-void tseng_terminate_acl(TsengPtr pTseng);
-
-/*
- * conversion from X ROPs to Microsoft ROPs.
- */
-
-int W32OpTable[] =
-{
- 0x00, /* Xclear 0 */
- 0x88, /* Xand src AND dst */
- 0x44, /* XandReverse src AND NOT dst */
- 0xcc, /* Xcopy src */
- 0x22, /* XandInverted NOT src AND dst */
- 0xaa, /* Xnoop dst */
- 0x66, /* Xxor src XOR dst */
- 0xee, /* Xor src OR dst */
- 0x11, /* Xnor NOT src AND NOT
dst */
- 0x99, /* Xequiv NOT src XOR dst */
- 0x55, /* Xinvert NOT dst */
- 0xdd, /* XorReverse src OR NOT dst */
- 0x33, /* XcopyInverted NOT src */
- 0xbb, /* XorInverted NOT src OR dst */
- 0x77, /* Xnand NOT src OR NOT dst
*/
- 0xff /* Xset 1 */
-};
-
-int W32OpTable_planemask[] =
-{
- 0x0a, /* Xclear 0 */
- 0x8a, /* Xand src AND dst */
- 0x4a, /* XandReverse src AND NOT dst */
- 0xca, /* Xcopy src */
- 0x2a, /* XandInverted NOT src AND dst */
- 0xaa, /* Xnoop dst */
- 0x6a, /* Xxor src XOR dst */
- 0xea, /* Xor src OR dst */
- 0x1a, /* Xnor NOT src AND NOT
dst */
- 0x9a, /* Xequiv NOT src XOR dst */
- 0x5a, /* Xinvert NOT dst */
- 0xda, /* XorReverse src OR NOT dst */
- 0x3a, /* XcopyInverted NOT src */
- 0xba, /* XorInverted NOT src OR dst */
- 0x7a, /* Xnand NOT src OR NOT dst
*/
- 0xfa /* Xset 1 */
-};
-
-int W32PatternOpTable[] =
-{
- 0x00, /* Xclear 0 */
- 0xa0, /* Xand pat AND dst */
- 0x50, /* XandReverse pat AND NOT dst */
- 0xf0, /* Xcopy pat */
- 0x0a, /* XandInverted NOT pat AND dst */
- 0xaa, /* Xnoop dst */
- 0x5a, /* Xxor pat XOR dst */
- 0xfa, /* Xor pat OR dst */
- 0x05, /* Xnor NOT pat AND NOT
dst */
- 0xa5, /* Xequiv NOT pat XOR dst */
- 0x55, /* Xinvert NOT dst */
- 0xf5, /* XorReverse pat OR NOT dst */
- 0x0f, /* XcopyInverted NOT pat */
- 0xaf, /* XorInverted NOT pat OR dst */
- 0x5f, /* Xnand NOT pat OR NOT dst
*/
- 0xff /* Xset 1 */
-};
-
-
-
-/**********************************************************************/
-
-void
-tseng_terminate_acl(TsengPtr pTseng)
-{
- /* only terminate when needed */
-/* if (*(volatile unsigned char *)ACL_ACCELERATOR_STATUS & 0x06) */
- {
- ACL_SUSPEND_TERMINATE(0x00);
- /* suspend any running operation */
- ACL_SUSPEND_TERMINATE(0x01);
- WAIT_ACL;
- ACL_SUSPEND_TERMINATE(0x00);
- /* ... and now terminate it */
- ACL_SUSPEND_TERMINATE(0x10);
- WAIT_ACL;
- ACL_SUSPEND_TERMINATE(0x00);
- }
-}
-
-void
-tseng_recover_timeout(TsengPtr pTseng)
-{
- if (!Is_ET6K) {
- ErrorF("trying to unlock......................................\n");
- MMIO_OUT32(pTseng->tsengCPU2ACLBase,0,0L); /* try unlocking the bus
when CPU-to-accel gets stuck */
- }
- if (Is_W32p) { /* flush the accelerator pipeline */
- ACL_SUSPEND_TERMINATE(0x00);
- ACL_SUSPEND_TERMINATE(0x02);
- ACL_SUSPEND_TERMINATE(0x00);
- }
-}
-
-void
-tseng_init_acl(ScrnInfoPtr pScrn)
-{
- TsengPtr pTseng = TsengPTR(pScrn);
-
- PDEBUG(" tseng_init_acl\n");
- /*
- * prepare some shortcuts for faster access to memory mapped registers
- */
-
- if (pTseng->UseLinMem) {
- pTseng->scratchMemBase = pTseng->FbBase +
pTseng->AccelColorBufferOffset;
- /*
- * we won't be using tsengCPU2ACLBase in linear memory mode anyway,
since
- * using the MMU apertures restricts the amount of useable video memory
- * to only 2MB, supposing we ONLY redirect MMU aperture 2 to the CPU.
- * (see data book W32p, page 207)
- */
- pTseng->tsengCPU2ACLBase = pTseng->FbBase + 0x200000; /* MMU aperture
2 */
- } else {
- /*
- * MMU 0 is used for the scratchpad (i.e. FG and BG colors).
- *
- * MMU 1 is used for the Imagewrite buffers. This code assumes those
- * buffers are back-to-back, with AccelImageWriteBufferOffsets[0]
- * being the first, and don't exceed 8kb (aperture size) in total
- * length.
- */
- pTseng->scratchMemBase = pTseng->FbBase + 0x18000L;
- MMIO_OUT32(pTseng->MMioBase, 0x00<<0, pTseng->AccelColorBufferOffset);
- MMIO_OUT32(pTseng->MMioBase, 0x04<<0,
pTseng->AccelImageWriteBufferOffsets[0]);
- /*
- * tsengCPU2ACLBase is used for CPUtoSCreen...() operations on < ET6000
devices
- */
- pTseng->tsengCPU2ACLBase = pTseng->FbBase + 0x1C000L; /* MMU aperture
2 */
- /* MMIO_IN32(pTseng->MMioBase, 0x08<<0) = 200000; *//* TEST */
- }
-#ifdef DEBUG
- ErrorF("MMioBase = 0x%x, scratchMemBase = 0x%x\n", pTseng->MMioBase,
pTseng->scratchMemBase);
-#endif
-
- /*
- * prepare the accelerator for some real work
- */
-
- tseng_terminate_acl(pTseng);
-
- ACL_INTERRUPT_STATUS(0xe); /* clear interrupts */
- ACL_INTERRUPT_MASK(0x04); /* disable interrupts, but enable
deadlock exit */
- ACL_INTERRUPT_STATUS(0x0);
- ACL_ACCELERATOR_STATUS_SET(0x0);
-
- if (Is_ET6K) {
- ACL_STEPPING_INHIBIT(0x0); /* Undefined at power-on, let all maps
(Src, Dst, Mix, Pat) step */
- ACL_6K_CONFIG(0x00); /* maximum performance -- what did you
think? */
- ACL_POWER_CONTROL(0x01); /* conserve power when ACL is idle */
- ACL_MIX_CONTROL(0x33);
- ACL_TRANSFER_DISABLE(0x00); /* Undefined at power-on, enable all
transfers */
- } else { /* W32i/W32p */
- ACL_RELOAD_CONTROL(0x0);
- ACL_SYNC_ENABLE(0x1); /* | 0x2 = 0WS ACL read. Yields up to
10% faster operation for small blits */
- ACL_ROUTING_CONTROL(0x00);
- }
-
- if (Is_W32p || Is_ET6K) {
- /* Enable the W32p startup bit and set use an eight-bit pixel depth */
- ACL_NQ_X_POSITION(0);
- ACL_NQ_Y_POSITION(0);
- ACL_PIXEL_DEPTH((pScrn->bitsPerPixel - 8) << 1);
- /* writing destination address will start ACL */
- ACL_OPERATION_STATE(0x10);
- } else {
- /* X, Y positions set to zero's for w32 and w32i */
- ACL_X_POSITION(0);
- ACL_Y_POSITION(0);
- ACL_OPERATION_STATE(0x0);
- /* if we ever use CPU-to-screen pixmap uploading on W32I or W32,
- * ACL_VIRTUAL_BUS_SIZE will need to be made dynamic (i.e. moved to
- * Setup() functions).
- *
- * VBS = 1 byte is faster than VBS = 4 bytes, since the ACL can
- * start processing as soon as the first byte arrives.
- */
- ACL_VIRTUAL_BUS_SIZE(0x00);
- }
- ACL_DESTINATION_Y_OFFSET(pScrn->displayWidth * pTseng->Bytesperpixel - 1);
- ACL_XY_DIRECTION(0);
-
- MMU_CONTROL(0x74);
-
- if (Is_W32p && pTseng->UseLinMem) {
- /*
- * Since the w32p revs C and D don't have any memory mapped when the
- * accelerator registers are used it is necessary to use the MMUs to
- * provide a semblance of linear memory. Fortunately on these chips
- * the MMU appertures are 1 megabyte each. So as long as we are
- * willing to only use 3 megs of video memory we can have some
- * acceleration. If we ever get the CPU-to-screen-color-expansion
- * stuff working then we will NOT need to sacrifice the extra 1MB
- * provided by MBP2, because we could do dynamic switching of the APT
- * bit in the MMU control register.
- *
- * On W32p rev c and d MBP2 is hardwired to 0x200000 when linear
- * memory mode is enabled. (On rev a it is programmable).
- *
- * W32p rev a and b have their first 2M mapped in the normal (non-MMU)
- * way, and MMU0 and MMU1, each 512 kb wide, can be used to access
- * another 1MB of memory. This totals to 3MB of mem. available in
- * linear memory when the accelerator is enabled.
- */
- if (Is_W32p_ab) {
- MMIO_OUT32(pTseng->MMioBase, 0x00<<0, 0x200000L);
- MMIO_OUT32(pTseng->MMioBase, 0x04<<0, 0x280000L);
- } else { /* rev C & D */
- MMIO_OUT32(pTseng->MMioBase, 0x00<<0, 0x0L);
- MMIO_OUT32 (pTseng->MMioBase, 0x04<<0, 0x100000L);
- }
- }
-}
diff --git a/src/tseng_acl.h b/src/tseng_acl.h
deleted file mode 100644
index 9402d58..0000000
--- a/src/tseng_acl.h
+++ /dev/null
@@ -1,232 +0,0 @@
-
-/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/tseng/tseng_acl.h,v 1.16
1998/08/29 05:43:37 dawes Exp $ */
-
-
-#ifndef _TSENG_ACL_H
-#define _TSENG_ACL_H
-
-/*
- * if NO_OPTIMIZE is set, some optimizations are disabled.
- *
- * What it basically tries to do is minimize the amounts of writes to
- * accelerator registers, since these are the ones that slow down small
- * operations a lot.
- */
-
-#undef NO_OPTIMIZE
-
-typedef volatile unsigned char *ByteP;
-typedef volatile unsigned short *WordP;
-typedef volatile unsigned *LongP;
-
-void tseng_recover_timeout(TsengPtr pTseng);
-
-/*
- * Shortcuts to Tseng memory-mapped accelerator-control registers
- */
-
-#if 0
-#endif
-
-#define MMU_CONTROL(x) MMIO_OUT8(pTseng->MMioBase, 0x13<<0, x)
-#define ACL_SUSPEND_TERMINATE(x) MMIO_OUT8(pTseng->MMioBase, 0x30<<0, x)
-#define ACL_OPERATION_STATE(x) MMIO_OUT8(pTseng->MMioBase, 0x31<<0, x)
-
-#define ACL_SYNC_ENABLE(x) MMIO_OUT8(pTseng->MMioBase, 0x32<<0, x)
- /* for ET6000, ACL_SYNC_ENABLE becomes ACL_6K_CONFIG */
-
-#define ACL_INTERRUPT_STATUS(x) \
- MMIO_OUT8(pTseng->MMioBase, 0x35<<0, x)
-#define ACL_INTERRUPT_MASK(x) MMIO_OUT8(pTseng->MMioBase, 0x34<<0, x)
-#define ACL_ACCELERATOR_STATUS (0x36 << 0)
-#define ACL_ACCELERATOR_STATUS_SET(x) \
- MMIO_OUT8(pTseng->MMioBase, ACL_ACCELERATOR_STATUS, x)
-#define ACL_WRITE_INTERFACE_VALID (0x33 << 0)
-
- /* and this is only for the ET6000 */
-#define ACL_POWER_CONTROL(x) MMIO_OUT8(pTseng->MMioBase, 0x37<<0, x)
-
- /* non-queued for w32p's and ET6000 */
-#define ACL_NQ_X_POSITION(x) MMIO_OUT16(pTseng->MMioBase, 0x38<<0, x)
-#define ACL_NQ_Y_POSITION(x) MMIO_OUT16(pTseng->MMioBase, 0x3A<<0, x)
- /* queued for w32 and w32i */
-#define ACL_X_POSITION(x) MMIO_OUT16(pTseng->MMioBase, 0x94<<0, x)
-#define ACL_Y_POSITION(x) MMIO_OUT16(pTseng->MMioBase, 0x96<<0, x)
-
-#define ACL_PATTERN_ADDRESS(x) MMIO_OUT32(pTseng->MMioBase, 0x80<<0, x)
-#define ACL_SOURCE_ADDRESS(x) MMIO_OUT32(pTseng->MMioBase, 0x84<<0, x)
-
-#define ACL_PATTERN_Y_OFFSET(x) MMIO_OUT16(pTseng->MMioBase, 0x88<<0, x)
-#define ACL_PATTERN_Y_OFFSET32(x) MMIO_OUT32(pTseng->MMioBase, 0x88<<0, x)
-#define ACL_SOURCE_Y_OFFSET(x) MMIO_OUT16(pTseng->MMioBase, 0x8A<<0, x)
-#define ACL_DESTINATION_Y_OFFSET(x) MMIO_OUT16(pTseng->MMioBase, 0x8C<<0, x)
-
- /* W32i */
-#define ACL_VIRTUAL_BUS_SIZE(x) MMIO_OUT8(pTseng->MMioBase, 0x8E<<0, x)
- /* w32p */
-#define ACL_PIXEL_DEPTH(x) MMIO_OUT8(pTseng->MMioBase, 0x8E<<0, x)
-
- /* w32 and w32i */
-#define ACL_XY_DIRECTION(x) MMIO_OUT8(pTseng->MMioBase, 0x8F<<0, x)
-
-#define ACL_PATTERN_WRAP(x) MMIO_OUT8(pTseng->MMioBase, 0x90<<0, x)
-#define ACL_PATTERN_WRAP32(x) MMIO_OUT32(pTseng->MMioBase, 0x90<<0, x)
-#define ACL_TRANSFER_DISABLE(x) MMIO_OUT8(pTseng->MMioBase, 0x91<<0, x) /*
ET6000 only */
-#define ACL_SOURCE_WRAP(x) MMIO_OUT8(pTseng->MMioBase, 0x92<<0, x)
-
-#define ACL_X_COUNT(x) MMIO_OUT16(pTseng->MMioBase, 0x98<<0, x)
-#define ACL_Y_COUNT(x) MMIO_OUT16(pTseng->MMioBase, 0x9A<<0, x)
-/* shortcut. not a real register */
-#define ACL_XY_COUNT(x) MMIO_OUT32(pTseng->MMioBase, 0x98<<0, x)
-
-#define ACL_ROUTING_CONTROL(x) MMIO_OUT8(pTseng->MMioBase, 0x9C<<0, x)
- /* for ET6000, ACL_ROUTING_CONTROL becomes ACL_MIX_CONTROL */
-#define ACL_RELOAD_CONTROL(x) MMIO_OUT8(pTseng->MMioBase, 0x9D<<0, x)
- /* for ET6000, ACL_RELOAD_CONTROL becomes ACL_STEPPING_INHIBIT */
-
-#define ACL_BACKGROUND_RASTER_OPERATION(x) MMIO_OUT8(pTseng->MMioBase,
0x9E<<0, x)
-#define ACL_FOREGROUND_RASTER_OPERATION(x) MMIO_OUT8(pTseng->MMioBase,
0x9F<<0, x)
-
-#define ACL_DESTINATION_ADDRESS(x) MMIO_OUT32(pTseng->MMioBase, 0xA0<<0, x)
-
- /* the following is for the w32p's only */
-#define ACL_MIX_ADDRESS(x) MMIO_OUT32(pTseng->MMioBase, 0xA4<<0, x)
-
-#define ACL_MIX_Y_OFFSET(x) MMIO_OUT16(pTseng->MMioBase, 0xA8<<0, x)
-#define ACL_ERROR_TERM(x) MMIO_OUT16(pTseng->MMioBase, 0xAA<<0, x)
-#define ACL_DELTA_MINOR(x) MMIO_OUT16(pTseng->MMioBase, 0xAC<<0, x)
-#define ACL_DELTA_MINOR32(x) MMIO_OUT32(pTseng->MMioBase, 0xAC<<0, x)
-#define ACL_DELTA_MAJOR(x) MMIO_OUT16(pTseng->MMioBase, 0xAE<<0, x)
-
- /* ET6000 only (trapezoids) */
-#define ACL_SECONDARY_EDGE(x) MMIO_OUT8(pTseng->MMioBase, 0x93<<0, x)
-#define ACL_SECONDARY_ERROR_TERM(x) MMIO_OUT16(pTseng->MMioBase, 0xB2<<0, x)
-#define ACL_SECONDARY_DELTA_MINOR(x) MMIO_OUT16(pTseng->MMioBase, 0xB4<<0, x)
-#define ACL_SECONDARY_DELTA_MINOR32(x) MMIO_OUT32(pTseng->MMioBase, 0xB4<<0, x)
-#define ACL_SECONDARY_DELTA_MAJOR(x) MMIO_OUT16(pTseng->MMioBase, 0xB6<<0, x)
-
-/* for ET6000: */
-#define ACL_6K_CONFIG ACL_SYNC_ENABLE
-
-/* for ET6000: */
-#define ACL_MIX_CONTROL ACL_ROUTING_CONTROL
-#define ACL_STEPPING_INHIBIT ACL_RELOAD_CONTROL
-
-
-/*
- * Some data structures for faster accelerator programming.
- */
-
-extern int W32OpTable[16];
-extern int W32OpTable_planemask[16];
-extern int W32PatternOpTable[16];
-
-/*
- * Some shortcuts.
- */
-
-#define MAX_WAIT_CNT 500000 /* how long we wait before we time out */
-#undef WAIT_VERBOSE /* if defined: print out how long we
waited */
-
-static __inline__ void
-tseng_wait(TsengPtr pTseng, int reg, char *name, unsigned char mask)
-{
- int cnt = MAX_WAIT_CNT;
-
- while ((MMIO_IN32(pTseng->MMioBase,reg)) & mask)
- if (--cnt < 0) {
- ErrorF("WAIT_%s: timeout.\n", name);
- tseng_recover_timeout(pTseng);
- break;
- }
-#ifdef WAIT_VERBOSE
- ErrorF("%s%d ", name, MAX_WAIT_CNT - cnt);
-#endif
-}
-
-#define WAIT_QUEUE tseng_wait(pTseng, ACL_ACCELERATOR_STATUS, "QUEUE", 0x1)
-
-/* This is only for W32p rev b...d */
-#define WAIT_INTERFACE tseng_wait(pTseng, ACL_WRITE_INTERFACE_VALID,
"INTERFACE", 0xf)
-
-#define WAIT_ACL tseng_wait(pTseng, ACL_ACCELERATOR_STATUS, "ACL", 0x2)
-
-#define WAIT_XY tseng_wait(pTseng, ACL_ACCELERATOR_STATUS, "XY", 0x4)
-
-#define SET_FUNCTION_BLT \
- if (Is_ET6K) \
- ACL_MIX_CONTROL(0x33); \
- else \
- ACL_ROUTING_CONTROL(0x00);
-
-#define SET_FUNCTION_BLT_TR \
- ACL_MIX_CONTROL(0x13);
-
-#define FBADDR(pTseng, x,y) ( (y) * pTseng->line_width + MULBPP(pTseng, x) )
-
-#define SET_FG_ROP(rop) \
- ACL_FOREGROUND_RASTER_OPERATION(W32OpTable[rop]);
-
-#define SET_FG_ROP_PLANEMASK(rop) \
- ACL_FOREGROUND_RASTER_OPERATION(W32OpTable_planemask[rop]);
-
-#define SET_BG_ROP(rop) \
- ACL_BACKGROUND_RASTER_OPERATION(W32PatternOpTable[rop]);
-
-#define SET_BG_ROP_TR(rop, bg_color) \
- if ((bg_color) == -1) /* transparent color expansion */ \
- ACL_BACKGROUND_RASTER_OPERATION(0xaa); \
- else \
- ACL_BACKGROUND_RASTER_OPERATION(W32PatternOpTable[rop]);
-
-#define SET_DELTA(Min, Maj) \
- ACL_DELTA_MINOR32(((Maj) << 16) + (Min))
-
-#define SET_SECONDARY_DELTA(Min, Maj) \
- ACL_SECONDARY_DELTA_MINOR(((Maj) << 16) + (Min))
-
-#ifdef NO_OPTIMIZE
-#define SET_XYDIR(dir) \
- ACL_XY_DIRECTION(dir);
-#else
-/*
- * only changing ACL_XY_DIRECTION when it needs to be changed avoids
- * unnecessary PCI bus writes, which are slow. This shows up very well
- * on consecutive small fills.
- */
-#define SET_XYDIR(dir) \
- if ((dir) != pTseng->tseng_old_dir) \
- pTseng->tseng_old_dir = (dir); \
- ACL_XY_DIRECTION(pTseng->tseng_old_dir);
-#endif
-
-#define SET_SECONDARY_XYDIR(dir) \
- ACL_SECONDARY_EDGE(dir);
-
-/* Must do 0x09 (in one operation) for the W32 */
-#define START_ACL(pTseng, dst) \
- ACL_DESTINATION_ADDRESS(dst); \
- if (Is_W32 || Is_W32i) ACL_OPERATION_STATE(0x09);
-
-/* START_ACL for the ET6000 */
-#define START_ACL_6(dst) \
- ACL_DESTINATION_ADDRESS(dst);
-
-#define START_ACL_CPU(pTseng, dst) \
- if (Is_W32 || Is_W32i) \
- MMIO_OUT32(pTseng->MMioBase, 0x08<<8,(CARD32)dst); /* writing to MMU2
will trigger accel at this address */ \
- else \
- ACL_DESTINATION_ADDRESS(dst);
-
-/* ACL_DESTINATION_ADDRESS(dst); should be enough for START_ACL_CPU */
-
-/***********************************************************************/
-
-void tseng_init_acl(ScrnInfoPtr pScrn);
-
-Bool TsengXAAInit(ScreenPtr pScreen);
-
-Bool TsengXAAInit_Colexp(ScrnInfoPtr pScrn);
-
-#endif
-
diff --git a/src/tseng_bank.c b/src/tseng_bank.c
deleted file mode 100644
index c201d4f..0000000
--- a/src/tseng_bank.c
+++ /dev/null
@@ -1,87 +0,0 @@
-
-/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/tseng/tseng_bank.c,v 1.2
1998/07/26 09:56:17 dawes Exp $ */
-
-#ifdef HAVE_CONFIG_H
-#include "config.h"
-#endif
-
-#include "tseng.h"
-
-/*
- * Tseng really screwed up when they decided to combine the read and write
- * bank selectors into one register. Now we need to cache the bank
- * registers, because IO reads are too expensive.
- */
-
-
-int
-ET4000W32SetRead(ScreenPtr pScreen, unsigned int iBank)
-{
- ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
- TsengPtr pTseng = TsengPTR(pScrn);
-
- pTseng->cache_SegSelL = (pTseng->cache_SegSelL & 0x0f) | (iBank << 4);
- pTseng->cache_SegSelH = (pTseng->cache_SegSelH & 0x03) | (iBank & 0x30);
- outb(0x3CB, pTseng->cache_SegSelH);
- outb(0x3CD, pTseng->cache_SegSelL);
- return 0;
-}
-
-int
-ET4000W32SetWrite(ScreenPtr pScreen, unsigned int iBank)
-{
- ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
- TsengPtr pTseng = TsengPTR(pScrn);
-
- pTseng->cache_SegSelL = (pTseng->cache_SegSelL & 0xf0) | (iBank & 0x0f);
- pTseng->cache_SegSelH = (pTseng->cache_SegSelH & 0x30) | (iBank >> 4);
- outb(0x3CB, pTseng->cache_SegSelH);
- outb(0x3CD, pTseng->cache_SegSelL);
- return 0;
-}
-
-int
-ET4000W32SetReadWrite(ScreenPtr pScreen, unsigned int iBank)
-{
- ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
- TsengPtr pTseng = TsengPTR(pScrn);
-
- pTseng->cache_SegSelL = (iBank & 0x0f) | (iBank << 4);
- pTseng->cache_SegSelH = (iBank & 0x30) | (iBank >> 4);
- outb(0x3CB, pTseng->cache_SegSelH);
- outb(0x3CD, pTseng->cache_SegSelL);
- return 0;
-}
-
-int
-ET4000SetRead(ScreenPtr pScreen, unsigned int iBank)
-{
- ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
- TsengPtr pTseng = TsengPTR(pScrn);
-
- pTseng->cache_SegSelL = (pTseng->cache_SegSelL & 0x0f) | (iBank << 4);
- outb(0x3CD, pTseng->cache_SegSelL);
- return 0;
-}
-
-int
-ET4000SetWrite(ScreenPtr pScreen, unsigned int iBank)
-{
- ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
- TsengPtr pTseng = TsengPTR(pScrn);
-
- pTseng->cache_SegSelL = (pTseng->cache_SegSelL & 0xf0) | (iBank & 0x0f);
- outb(0x3CD, pTseng->cache_SegSelL);
- return 0;
-}
-
-int
-ET4000SetReadWrite(ScreenPtr pScreen, unsigned int iBank)
-{
- ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
- TsengPtr pTseng = TsengPTR(pScrn);
-
- pTseng->cache_SegSelL = (iBank & 0x0f) | (iBank << 4);
- outb(0x3CD, pTseng->cache_SegSelL);
- return 0;
-}
diff --git a/src/tseng_clock.c b/src/tseng_clock.c
deleted file mode 100644
index 71c9e34..0000000
--- a/src/tseng_clock.c
+++ /dev/null
@@ -1,509 +0,0 @@
-
-/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/tseng/tseng_clock.c,v 1.18
2003/11/03 05:11:44 tsi Exp $ */
-
-#ifdef HAVE_CONFIG_H
-#include "config.h"
-#endif
-
-/*
- *
- * Copyright 1993-1997 The XFree86 Project, Inc.
- *
- */
-/**
- ** Clock setting methods for Tseng chips
- **
- ** The *ClockSelect() fucntions are ONLY used used for clock probing!
- ** Setting the actual clock is done in TsengRestore().
- **/
-
-#include "tseng.h"
-
-static Bool Tseng_ET4000ClockSelect(ScrnInfoPtr pScrn, int no);
-static Bool Tseng_LegendClockSelect(ScrnInfoPtr pScrn, int no);
-
-
-static SymTabRec TsengClockChips[] =
-{
- {CLOCKCHIP_ICD2061A, "icd2061a"},
- {CLOCKCHIP_ET6000, "et6000"},
- {CLOCKCHIP_ICS5341, "ics5341"},
- {CLOCKCHIP_ICS5301, "ics5301"},
- {CLOCKCHIP_CH8398, "ch8398"},
- {CLOCKCHIP_STG1703, "stg1703"},
- {-1, NULL}
-};
-
-Bool
-Tseng_check_clockchip(ScrnInfoPtr pScrn)
-{
- MessageType from;
- TsengPtr pTseng = TsengPTR(pScrn);
-
- PDEBUG(" Tseng_check_clockchip\n");
-
- if (pTseng->pEnt->device->clockchip && *pTseng->pEnt->device->clockchip) {
- /* clockchip given as a string in the config file */
- pScrn->clockchip = pTseng->pEnt->device->clockchip;
- pTseng->ClockChip =
- (t_clockchip_type)xf86StringToToken(TsengClockChips, pScrn->clockchip);
- if (pTseng->ClockChip == CLOCKCHIP_DEFAULT) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Unknown clockchip: \"%s\"\n",
- pScrn->clockchip);
- return FALSE;
- }
- from = X_CONFIG;
- } else {
- /* ramdac probe already defined pTseng->ClockChip */
- pScrn->clockchip = (char *)xf86TokenToString(TsengClockChips,
pTseng->ClockChip);
- from = X_PROBED;
- }
- xf86DrvMsg(pScrn->scrnIndex, from, "Clockchip: \"%s\"\n",
- pScrn->clockchip);
-
- return TRUE;
-}
-
-
-void tseng_clock_setup(ScrnInfoPtr pScrn)
-{
- TsengPtr pTseng = TsengPTR(pScrn);
- int iobase = VGAHW_GET_IOBASE();
- MessageType from;
- int dacspeed, mem_bw;
- Bool forceSpeed = FALSE;
- int i;
-
- PDEBUG(" tseng_clock_setup\n");
-
- /*
- * Memory bandwidth is important in > 8bpp modes, especially on ET4000
- *
- * This code evaluates a video mode with respect to requested dot clock
- * (depends on the VGA chip and the RAMDAC) and the resulting bandwidth
- * demand on memory (which in turn depends on color depth).
- *
- * For each mode, the minimum of max data transfer speed (dot clock
- * limit) and memory bandwidth determines if the mode is allowed.
- *
- * We should also take acceleration into account: accelerated modes
- * strain the bandwidth heavily, because they cause lots of random
- * acesses to video memory, which is bad for bandwidth due to smaller
- * page-mode memory requests.
- */
-
- /* Set the min pixel clock */
- pTseng->MinClock = 12000; /* XXX Guess, need to check this */
-
- /*
- * If the user has specified ramdac speed in the XF86Config
- * file, we respect that setting.
- */
- if (pTseng->pEnt->device->dacSpeeds[0]) {
- from = X_CONFIG;
- forceSpeed = TRUE;
- switch (pScrn->bitsPerPixel) {
- default:
- case 1:
- case 4:
- case 8:
- dacspeed = pTseng->pEnt->device->dacSpeeds[DAC_BPP8];
- break;
- case 16:
- dacspeed = pTseng->pEnt->device->dacSpeeds[DAC_BPP16];
- break;
- case 24:
- dacspeed = pTseng->pEnt->device->dacSpeeds[DAC_BPP24];
- break;
- case 32:
- dacspeed = pTseng->pEnt->device->dacSpeeds[DAC_BPP32];
- break;
- }
- pTseng->max_vco_freq = pTseng->pEnt->device->dacSpeeds[0]*2+1;
- /* if a bpp-specific DacSpeed is not defined, use the "default" one
(=8bpp) */
- if (dacspeed == 0)
- dacspeed = pTseng->pEnt->device->dacSpeeds[0];
- } else {
- from = X_PROBED;
- forceSpeed = FALSE;
- /* default */
- dacspeed = MAX_TSENG_CLOCK;
- /*
- * According to Tseng (about the ET6000):
- * "Besides the 135 MHz maximum pixel clock frequency, the other limit
has to
- * do with where you get FIFO breakdown (usually appears as stray
horizontal
- * lines on the screen). Assuming the accelerator is running steadily
doing a
- * worst case operation, to avoid FIFO breakdown you should keep the
product
- * pixel_clock*(bytes/pixel) <= 225 MHz . This is based on an XCLK
- * (system/memory) clock of 92 MHz (which is what we currently use) and
- * a value in the RAS/CAS Configuration register (CFG 44) of either 015h
- * or 014h (depending on the type of MDRAM chips). Also, the FIFO low
- * threshold control bit (bit 4 of CFG 41) should be set for modes where
- * pixel_clock*(bytes/pixel) > 130 MHz . These limits are for the
- * current ET6000 chips. The ET6100 will raise the pixel clock limit
- * to 175 MHz and the pixel_clock*(bytes/pixel) FIFO breakdown limit
- * to about 275 MHz."
- */
- if (Is_ET6100) {
- dacspeed = 175000;
- mem_bw = 280000; /* 275000 is _just_ not enough
for 1152x864x24 @ 70Hz */
- } else if (Is_ET6000) {
- dacspeed = 135000;
- mem_bw = 225000;
- } else {
- if ( (pTseng->DacInfo.DacPort16) &&
- (pScrn->bitsPerPixel == 8) &&
- (!(DAC_is_GenDAC && pTseng->NoClockchip)) ) {
- dacspeed = 135000; /* we can do PIXMUX */
- }
- mem_bw = 90000;
- if (pScrn->videoRam > 1024)
- mem_bw = 150000; /* interleaved DRAM gives 70%
more bandwidth */
- }
- pTseng->max_vco_freq = dacspeed*2+1;
- /*
- * "dacspeed" is the theoretical limit imposed by the RAMDAC.
- * "mem_bw" is the max memory bandwidth in mb/sec available
- * for the pixel FIFO.
- * The lowest of the two determines the actual pixel clock limit.
- */
- dacspeed = min(dacspeed, (mem_bw / pTseng->Bytesperpixel));
- }
-
- /*
- * Setup the ClockRanges, which describe what clock ranges are available,
- * and what sort of modes they can be used for.
- *
- * First, we set up the default case, and modify it later if needed.
- */
- pTseng->clockRange[0] = xnfcalloc(sizeof(ClockRange), 1);
- pTseng->clockRange[0]->next = NULL;
- pTseng->clockRange[0]->minClock = pTseng->MinClock;
- pTseng->clockRange[0]->maxClock = dacspeed;
- pTseng->clockRange[0]->clockIndex = -1; /* programmable -- not used */
- pTseng->clockRange[0]->interlaceAllowed = TRUE;
- pTseng->clockRange[0]->doubleScanAllowed = TRUE;
- pTseng->clockRange[0]->ClockMulFactor = 1;
- pTseng->clockRange[0]->ClockDivFactor = 1;
- pTseng->clockRange[0]->PrivFlags = TSENG_MODE_NORMAL;
-
- /*
- * Handle PIXMUX modes.
- *
- * NOTE: We disable PIXMUX when clockchip programming on the GenDAC
- * family is disabled. PIXMUX requires that the N2 post-divider in the
- * PLL clock programming word is >= 2, which is not always true for the
- * default (BIOS) clocks programmed in the 8 clock registers.
- */
- if ( (pTseng->DacInfo.DacPort16) &&
- (pScrn->bitsPerPixel == 8) &&
- (!(DAC_is_GenDAC && pTseng->NoClockchip)) ) {
- pTseng->clockRange[0]->maxClock = MAX_TSENG_CLOCK;
- /* set up 2nd clock range for PIXMUX modes */
- pTseng->clockRange[1] = xnfcalloc(sizeof(ClockRange), 1);
- pTseng->clockRange[0]->next = pTseng->clockRange[1];
- pTseng->clockRange[1]->next = NULL;
- pTseng->clockRange[1]->minClock = 75000;
- pTseng->clockRange[1]->maxClock = dacspeed;
- pTseng->clockRange[1]->clockIndex = -1; /* programmable -- not
used */
- pTseng->clockRange[1]->interlaceAllowed = TRUE;
- pTseng->clockRange[1]->doubleScanAllowed = TRUE;
- pTseng->clockRange[1]->ClockMulFactor = 1;
- pTseng->clockRange[1]->ClockDivFactor = 2;
- pTseng->clockRange[1]->PrivFlags = TSENG_MODE_PIXMUX;
- }
-
- /*
- * Handle 16/24/32 bpp modes that require some form of clock scaling. We
- * can have either 8-bit DACs that require "bytesperpixel" clocks per
- * pixel, or 16-bit DACs that can transport 8 or 16 bits per clock.
- */
- if ((pTseng->Bytesperpixel > 1) && (!Is_ET6K)) {
- /* in either 8 or 16-bit DAC case, we can use an 8-bit interface */
- pTseng->clockRange[0]->maxClock = (forceSpeed) ? dacspeed :
- min(MAX_TSENG_CLOCK / pTseng->Bytesperpixel, dacspeed);
- pTseng->clockRange[0]->ClockMulFactor = pTseng->Bytesperpixel;
- pTseng->clockRange[0]->ClockDivFactor = 1;
- /* in addition, 16-bit DACs can also transport 2 bytes per clock */
- if (pTseng->DacInfo.DacPort16) {
- pTseng->clockRange[1] = xnfcalloc(sizeof(ClockRange), 1);
- pTseng->clockRange[0]->next = pTseng->clockRange[1];
- pTseng->clockRange[1]->next = NULL;
- pTseng->clockRange[1]->minClock = pTseng->MinClock;
- pTseng->clockRange[1]->maxClock = (forceSpeed) ? dacspeed :
- min((MAX_TSENG_CLOCK * 2) / pTseng->Bytesperpixel, dacspeed);
- pTseng->clockRange[1]->clockIndex = -1; /* programmable -- not
used */
- pTseng->clockRange[1]->interlaceAllowed = TRUE;
- pTseng->clockRange[1]->doubleScanAllowed = TRUE;
- pTseng->clockRange[1]->ClockMulFactor = pTseng->Bytesperpixel;
- pTseng->clockRange[1]->ClockDivFactor = 2;
- pTseng->clockRange[1]->PrivFlags = TSENG_MODE_DACBUS16;
- }
- }
-
- if (pTseng->clockRange[1])
- pTseng->MaxClock = pTseng->clockRange[1]->maxClock;
- else
- pTseng->MaxClock = pTseng->clockRange[0]->maxClock;
-
- xf86DrvMsg(pScrn->scrnIndex, X_DEFAULT, "Min pixel clock is %d MHz\n",
- pTseng->MinClock / 1000);
- xf86DrvMsg(pScrn->scrnIndex, from, "Max pixel clock is %d MHz\n",
- pTseng->MaxClock / 1000);
-
- /* Memory clock setup */
- pTseng->MClkInfo.Set = FALSE;
- /* Only set MemClk if appropriate for the ramdac */
- if (pTseng->MClkInfo.Programmable) {
- from = X_PROBED;
- if (pTseng->MemClk > 0) {
- if ((pTseng->MemClk < pTseng->MClkInfo.min)
- || (pTseng->MemClk > pTseng->MClkInfo.max)) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "MCLK %d MHz out of range (=%d..%d); not changed!\n",
- pTseng->MemClk / 1000,
- pTseng->MClkInfo.min / 1000,
- pTseng->MClkInfo.max / 1000);
- } else {
- pTseng->MClkInfo.MemClk = pTseng->MemClk;
- pTseng->MClkInfo.Set = TRUE;
- from = X_CONFIG;
- }
- }
- xf86DrvMsg(pScrn->scrnIndex, from, "MCLK used is %d MHz\n",
- pTseng->MClkInfo.MemClk / 1000);
- }
-
- /*
- * Set up the list-of-clocks stuff if we don't have a programmable
- * clockchip (the RAMDAC probe sets the pScrn->progClock field).
- */
- if (!pScrn->progClock) {
- int NoClocks;
- Bool (*TsengClockSelect)(ScrnInfoPtr, int);
-
- /* first determine how many clocks there are (or can be) */
- if (pTseng->Legend) {
- TsengClockSelect = Tseng_LegendClockSelect;
- NoClocks = 32;
- } else {
- TsengClockSelect = Tseng_ET4000ClockSelect;
- /*
- * The CH8398 RAMDAC uses CS3 for register selection (RS2), not for
clock selection.
- * The GenDAC family only has 8 clocks. Together with MCLK/2,
that's 16 clocks.
- */
- if ( (!Is_stdET4K)
- && (!DAC_is_GenDAC) && (pTseng->DacInfo.DacType != CH8398_DAC) )
- NoClocks = 32;
- else
--
To UNSUBSCRIBE, email to [EMAIL PROTECTED]
with a subject of "unsubscribe". Trouble? Contact [EMAIL PROTECTED]
