configure.ac | 3 man/radeon.man | 120 ++++-- src/AtomBios/CD_Operations.c | 8 src/AtomBios/includes/atombios.h | 11 src/Makefile.am | 4 src/ati_pciids_gen.h | 29 + src/atombios_crtc.c | 14 src/atombios_output.c | 439 +++++++++++++--------- src/legacy_crtc.c | 44 +- src/legacy_output.c | 17 src/pcidb/ati_pciids.csv | 43 +- src/radeon.h | 56 ++ src/radeon_accel.c | 5 src/radeon_atombios.c | 224 +++++++---- src/radeon_atombios.h | 6 src/radeon_bios.c | 19 src/radeon_chipinfo_gen.h | 29 + src/radeon_chipset_gen.h | 43 +- src/radeon_commonfuncs.c | 123 +++--- src/radeon_crtc.c | 51 ++ src/radeon_dri.c | 6 src/radeon_driver.c | 7 src/radeon_drm.h | 26 - src/radeon_exa.c | 61 +-- src/radeon_exa_funcs.c | 15 src/radeon_exa_render.c | 174 +++++--- src/radeon_modes.c | 65 +++ src/radeon_output.c | 68 ++- src/radeon_pci_chipset_gen.h | 29 + src/radeon_pci_device_match_gen.h | 29 + src/radeon_probe.c | 2 src/radeon_probe.h | 8 src/radeon_reg.h | 222 ++++++----- src/radeon_textured_video.c | 75 +++ src/radeon_textured_videofuncs.c | 735 ++++++++++++++++++++++++++++++-------- src/radeon_video.c | 32 + src/radeon_video.h | 10 37 files changed, 2061 insertions(+), 791 deletions(-)
New commits: commit 631123d144d088d4f77a0599c34deaa31d551d71 Author: Dave Airlie <[email protected]> Date: Tue Dec 23 10:08:46 2008 +1000 radeon: update to 6.9.0.91 do a prerelease for end of year. diff --git a/configure.ac b/configure.ac index 5ffe0d9..4b9c6b1 100644 --- a/configure.ac +++ b/configure.ac @@ -22,7 +22,7 @@ AC_PREREQ(2.57) AC_INIT([xf86-video-ati], - 6.9.0, + 6.9.0.91, [https://bugs.freedesktop.org/enter_bug.cgi?product=xorg], xf86-video-ati) commit 047f7603174f6047090f4fafbe6488d697eb78bc Author: Dave Airlie <[email protected]> Date: Tue Dec 23 08:16:25 2008 +1000 radeon: pass distcheck diff --git a/src/Makefile.am b/src/Makefile.am index d65a3e4..a13bfad 100644 --- a/src/Makefile.am +++ b/src/Makefile.am @@ -130,18 +130,16 @@ EXTRA_DIST = \ radeon_textured_videofuncs.c \ ati.h \ ativersion.h \ + bicubic_table.h \ generic_bus.h \ - radeon_common.h \ radeon_commonfuncs.c \ radeon_dri.h \ - radeon_dripriv.h \ radeon_exa_render.c \ radeon_exa_funcs.c \ radeon.h \ radeon_macros.h \ radeon_probe.h \ radeon_reg.h \ - radeon_sarea.h \ radeon_version.h \ radeon_video.h \ radeon_tv.h \ commit c0c33dab44e6966b1702d4e8cfba3537fc6e2d5c Author: Patrick Haller <[email protected]> Date: Mon Dec 22 03:06:23 2008 -0500 Fix off by one in EXA composite limit checking Patch from Patrick, with some updates from me: - fix r200 limits - note about r100 limits diff --git a/src/radeon_exa_render.c b/src/radeon_exa_render.c index 55e55be..c285109 100644 --- a/src/radeon_exa_render.c +++ b/src/radeon_exa_render.c @@ -320,7 +320,11 @@ static Bool R100CheckCompositeTexture(PicturePtr pPict, int unit) int h = pPict->pDrawable->height; int i; - if ((w > 0x7ff) || (h > 0x7ff)) + /* r100 limit should be 2048, there are issues with 2048 + * see 197a62704742a4a19736c2637ac92d1dc5ab34ed + */ + + if ((w > 2047) || (h > 2047)) RADEON_FALLBACK(("Picture w/h too large (%dx%d)\n", w, h)); for (i = 0; i < sizeof(R100TexFormats) / sizeof(R100TexFormats[0]); i++) { @@ -456,10 +460,14 @@ static Bool R100CheckComposite(int op, PicturePtr pSrcPicture, if (!pSrcPicture->pDrawable) return FALSE; + /* r100 limit should be 2048, there are issues with 2048 + * see 197a62704742a4a19736c2637ac92d1dc5ab34ed + */ + pSrcPixmap = RADEONGetDrawablePixmap(pSrcPicture->pDrawable); - if (pSrcPixmap->drawable.width >= 2048 || - pSrcPixmap->drawable.height >= 2048) { + if (pSrcPixmap->drawable.width > 2047 || + pSrcPixmap->drawable.height > 2047) { RADEON_FALLBACK(("Source w/h too large (%d,%d).\n", pSrcPixmap->drawable.width, pSrcPixmap->drawable.height)); @@ -467,8 +475,8 @@ static Bool R100CheckComposite(int op, PicturePtr pSrcPicture, pDstPixmap = RADEONGetDrawablePixmap(pDstPicture->pDrawable); - if (pDstPixmap->drawable.width >= 2048 || - pDstPixmap->drawable.height >= 2048) { + if (pDstPixmap->drawable.width > 2047 || + pDstPixmap->drawable.height > 2047) { RADEON_FALLBACK(("Dest w/h too large (%d,%d).\n", pDstPixmap->drawable.width, pDstPixmap->drawable.height)); @@ -477,8 +485,8 @@ static Bool R100CheckComposite(int op, PicturePtr pSrcPicture, if (pMaskPicture) { PixmapPtr pMaskPixmap = RADEONGetDrawablePixmap(pMaskPicture->pDrawable); - if (pMaskPixmap->drawable.width >= 2048 || - pMaskPixmap->drawable.height >= 2048) { + if (pMaskPixmap->drawable.width > 2047 || + pMaskPixmap->drawable.height > 2047) { RADEON_FALLBACK(("Mask w/h too large (%d,%d).\n", pMaskPixmap->drawable.width, pMaskPixmap->drawable.height)); @@ -531,7 +539,7 @@ static Bool FUNC_NAME(R100PrepareComposite)(int op, return FALSE; if (pDstPicture->format == PICT_a8 && RadeonBlendOp[op].dst_alpha) - RADEON_FALLBACK("Can't dst alpha blend A8\n"); + RADEON_FALLBACK("Can't dst alpha blend A8\n"); if (pMask) info->accel_state->has_mask = TRUE; @@ -635,7 +643,7 @@ static Bool R200CheckCompositeTexture(PicturePtr pPict, int unit) int h = pPict->pDrawable->height; int i; - if ((w > 0x7ff) || (h > 0x7ff)) + if ((w > 2048) || (h > 2048)) RADEON_FALLBACK(("Picture w/h too large (%dx%d)\n", w, h)); for (i = 0; i < sizeof(R200TexFormats) / sizeof(R200TexFormats[0]); i++) @@ -762,8 +770,8 @@ static Bool R200CheckComposite(int op, PicturePtr pSrcPicture, PicturePtr pMaskP pSrcPixmap = RADEONGetDrawablePixmap(pSrcPicture->pDrawable); - if (pSrcPixmap->drawable.width >= 2048 || - pSrcPixmap->drawable.height >= 2048) { + if (pSrcPixmap->drawable.width > 2048 || + pSrcPixmap->drawable.height > 2048) { RADEON_FALLBACK(("Source w/h too large (%d,%d).\n", pSrcPixmap->drawable.width, pSrcPixmap->drawable.height)); @@ -771,8 +779,8 @@ static Bool R200CheckComposite(int op, PicturePtr pSrcPicture, PicturePtr pMaskP pDstPixmap = RADEONGetDrawablePixmap(pDstPicture->pDrawable); - if (pDstPixmap->drawable.width >= 2048 || - pDstPixmap->drawable.height >= 2048) { + if (pDstPixmap->drawable.width > 2048 || + pDstPixmap->drawable.height > 2048) { RADEON_FALLBACK(("Dest w/h too large (%d,%d).\n", pDstPixmap->drawable.width, pDstPixmap->drawable.height)); @@ -781,8 +789,8 @@ static Bool R200CheckComposite(int op, PicturePtr pSrcPicture, PicturePtr pMaskP if (pMaskPicture) { PixmapPtr pMaskPixmap = RADEONGetDrawablePixmap(pMaskPicture->pDrawable); - if (pMaskPixmap->drawable.width >= 2048 || - pMaskPixmap->drawable.height >= 2048) { + if (pMaskPixmap->drawable.width > 2048 || + pMaskPixmap->drawable.height > 2048) { RADEON_FALLBACK(("Mask w/h too large (%d,%d).\n", pMaskPixmap->drawable.width, pMaskPixmap->drawable.height)); @@ -831,7 +839,7 @@ static Bool FUNC_NAME(R200PrepareComposite)(int op, PicturePtr pSrcPicture, return FALSE; if (pDstPicture->format == PICT_a8 && RadeonBlendOp[op].dst_alpha) - RADEON_FALLBACK("Can't dst alpha blend A8\n"); + RADEON_FALLBACK("Can't dst alpha blend A8\n"); if (pMask) info->accel_state->has_mask = TRUE; @@ -1054,7 +1062,7 @@ static Bool FUNC_NAME(R300TextureSetup)(PicturePtr pPict, PixmapPtr pPix, txfilter |= R300_TX_CLAMP_T(R300_TX_CLAMP_WRAP); else txfilter |= R300_TX_CLAMP_T(R300_TX_CLAMP_CLAMP_GL); - + txfilter |= (unit << R300_TX_ID_SHIFT); switch (pPict->filter) { @@ -1121,8 +1129,8 @@ static Bool R300CheckComposite(int op, PicturePtr pSrcPicture, PicturePtr pMaskP max_dst_h = 2560; } - if (pSrcPixmap->drawable.width >= max_tex_w || - pSrcPixmap->drawable.height >= max_tex_h) { + if (pSrcPixmap->drawable.width > max_tex_w || + pSrcPixmap->drawable.height > max_tex_h) { RADEON_FALLBACK(("Source w/h too large (%d,%d).\n", pSrcPixmap->drawable.width, pSrcPixmap->drawable.height)); @@ -1130,8 +1138,8 @@ static Bool R300CheckComposite(int op, PicturePtr pSrcPicture, PicturePtr pMaskP pDstPixmap = RADEONGetDrawablePixmap(pDstPicture->pDrawable); - if (pDstPixmap->drawable.width >= max_dst_w || - pDstPixmap->drawable.height >= max_dst_h) { + if (pDstPixmap->drawable.width > max_dst_w || + pDstPixmap->drawable.height > max_dst_h) { RADEON_FALLBACK(("Dest w/h too large (%d,%d).\n", pDstPixmap->drawable.width, pDstPixmap->drawable.height)); @@ -1140,8 +1148,8 @@ static Bool R300CheckComposite(int op, PicturePtr pSrcPicture, PicturePtr pMaskP if (pMaskPicture) { PixmapPtr pMaskPixmap = RADEONGetDrawablePixmap(pMaskPicture->pDrawable); - if (pMaskPixmap->drawable.width >= max_tex_w || - pMaskPixmap->drawable.height >= max_tex_h) { + if (pMaskPixmap->drawable.width > max_tex_w || + pMaskPixmap->drawable.height > max_tex_h) { RADEON_FALLBACK(("Mask w/h too large (%d,%d).\n", pMaskPixmap->drawable.width, pMaskPixmap->drawable.height)); commit d01a609a2b07da4ca0f182e79459432584ec61f6 Author: Alex Deucher <[email protected]> Date: Mon Dec 22 02:18:43 2008 -0500 R3xx-R5xx: better fix for xv primitive tearing issues R5xx: always use single clipped triangle R3xx/R4xx: use single clipped triangle up to guardband limit, then use quad. diff --git a/src/radeon_textured_videofuncs.c b/src/radeon_textured_videofuncs.c index 410430c..2fe852d 100644 --- a/src/radeon_textured_videofuncs.c +++ b/src/radeon_textured_videofuncs.c @@ -1486,16 +1486,30 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv pPriv->drw_y + pPriv->dst_h, pPriv->vsync); - BEGIN_ACCEL(2); - OUT_ACCEL_REG(R300_SC_SCISSOR0, ((0 << R300_SCISSOR_X_SHIFT) | - (0 << R300_SCISSOR_Y_SHIFT))); - OUT_ACCEL_REG(R300_SC_SCISSOR1, ((8191 << R300_SCISSOR_X_SHIFT) | - (8191 << R300_SCISSOR_Y_SHIFT))); - FINISH_ACCEL(); + /* + * Rendering of the actual polygon is done in two different + * ways depending on chip generation: + * + * < R300: + * + * These chips can render a rectangle in one pass, so + * handling is pretty straight-forward. + * + * >= R300: + * + * These chips can accept a quad, but will render it as + * two triangles which results in a diagonal tear. Instead + * We render a single, large triangle and use the scissor + * functionality to restrict it to the desired rectangle. + * Due to guardband limits on r3xx/r4xx, we can only use + * the single triangle up to 2880 pixels; above that we + * render as a quad. + */ while (nBox--) { int srcX, srcY, srcw, srch; int dstX, dstY, dstw, dsth; + Bool use_quad = FALSE; dstX = pBox->x1 + dstxoff; dstY = pBox->y1 + dstyoff; dstw = pBox->x2 - pBox->x1; @@ -1514,6 +1528,28 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv ErrorF("src: %d, %d, %d, %d\n", srcX, srcY, srcw, srch); #endif + if (IS_R300_3D || IS_R500_3D) { + if (IS_R300_3D && ((dstw > 1440) || (dsth > 1440))) + use_quad = TRUE; + /* + * Set up the scissor area to that of the output size. + */ + BEGIN_ACCEL(2); + if (IS_R300_3D) { + /* R300 has an offset */ + OUT_ACCEL_REG(R300_SC_SCISSOR0, (((dstX + 1088) << R300_SCISSOR_X_SHIFT) | + ((dstY + 1088) << R300_SCISSOR_Y_SHIFT))); + OUT_ACCEL_REG(R300_SC_SCISSOR1, (((dstX + dstw + 1088 - 1) << R300_SCISSOR_X_SHIFT) | + ((dstY + dsth + 1088 - 1) << R300_SCISSOR_Y_SHIFT))); + } else { + OUT_ACCEL_REG(R300_SC_SCISSOR0, (((dstX) << R300_SCISSOR_X_SHIFT) | + ((dstY) << R300_SCISSOR_Y_SHIFT))); + OUT_ACCEL_REG(R300_SC_SCISSOR1, (((dstX + dstw - 1) << R300_SCISSOR_X_SHIFT) | + ((dstY + dsth - 1) << R300_SCISSOR_Y_SHIFT))); + } + FINISH_ACCEL(); + } + #ifdef ACCEL_CP if (info->ChipFamily < CHIP_FAMILY_R200) { BEGIN_RING(3 * vtx_count + 3); @@ -1527,12 +1563,21 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE | (3 << RADEON_CP_VC_CNTL_NUM_SHIFT)); } else if (IS_R300_3D || IS_R500_3D) { - BEGIN_RING(4 * vtx_count + 4); - OUT_RING(CP_PACKET3(R200_CP_PACKET3_3D_DRAW_IMMD_2, - 4 * vtx_count)); - OUT_RING(RADEON_CP_VC_CNTL_PRIM_TYPE_QUAD_LIST | - RADEON_CP_VC_CNTL_PRIM_WALK_RING | - (4 << RADEON_CP_VC_CNTL_NUM_SHIFT)); + if (use_quad) { + BEGIN_RING(4 * vtx_count + 4); + OUT_RING(CP_PACKET3(R200_CP_PACKET3_3D_DRAW_IMMD_2, + 4 * vtx_count)); + OUT_RING(RADEON_CP_VC_CNTL_PRIM_TYPE_QUAD_LIST | + RADEON_CP_VC_CNTL_PRIM_WALK_RING | + (4 << RADEON_CP_VC_CNTL_NUM_SHIFT)); + } else { + BEGIN_RING(3 * vtx_count + 4); + OUT_RING(CP_PACKET3(R200_CP_PACKET3_3D_DRAW_IMMD_2, + 3 * vtx_count)); + OUT_RING(RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST | + RADEON_CP_VC_CNTL_PRIM_WALK_RING | + (3 << RADEON_CP_VC_CNTL_NUM_SHIFT)); + } } else { BEGIN_RING(3 * vtx_count + 2); OUT_RING(CP_PACKET3(R200_CP_PACKET3_3D_DRAW_IMMD_2, @@ -1542,9 +1587,12 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv (3 << RADEON_CP_VC_CNTL_NUM_SHIFT)); } #else /* ACCEL_CP */ - if (IS_R300_3D || IS_R500_3D) - BEGIN_ACCEL(2 + vtx_count * 4); - else + if (IS_R300_3D || IS_R500_3D) { + if (use_quad) + BEGIN_ACCEL(2 + vtx_count * 4); + else + BEGIN_ACCEL(2 + vtx_count * 3); + } else BEGIN_ACCEL(1 + vtx_count * 3); if (info->ChipFamily < CHIP_FAMILY_R200) @@ -1552,11 +1600,16 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv RADEON_VF_PRIM_WALK_DATA | RADEON_VF_RADEON_MODE | (3 << RADEON_VF_NUM_VERTICES_SHIFT))); - else if (IS_R300_3D || IS_R500_3D) - OUT_ACCEL_REG(RADEON_SE_VF_CNTL, (RADEON_VF_PRIM_TYPE_QUAD_LIST | - RADEON_VF_PRIM_WALK_DATA | - (4 << RADEON_VF_NUM_VERTICES_SHIFT))); - else + else if (IS_R300_3D || IS_R500_3D) { + if (use_quad) + OUT_ACCEL_REG(RADEON_SE_VF_CNTL, (RADEON_VF_PRIM_TYPE_QUAD_LIST | + RADEON_VF_PRIM_WALK_DATA | + (4 << RADEON_VF_NUM_VERTICES_SHIFT))); + else + OUT_ACCEL_REG(RADEON_SE_VF_CNTL, (RADEON_VF_PRIM_TYPE_TRIANGLE_LIST | + RADEON_VF_PRIM_WALK_DATA | + (3 << RADEON_VF_NUM_VERTICES_SHIFT))); + } else OUT_ACCEL_REG(RADEON_SE_VF_CNTL, (RADEON_VF_PRIM_TYPE_RECTANGLE_LIST | RADEON_VF_PRIM_WALK_DATA | (3 << RADEON_VF_NUM_VERTICES_SHIFT))); @@ -1567,6 +1620,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv * This code is only executed on >= R300, so we don't * have to deal with the legacy handling. */ + if (use_quad) { VTX_OUT_FILTER((float)dstX, (float)dstY, (float)srcX / info->accel_state->texW[0], (float)srcY / info->accel_state->texH[0], (float)srcX + 0.5, (float)srcY + 0.5); @@ -1579,27 +1633,52 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv VTX_OUT_FILTER((float)(dstX + dstw), (float)dstY, (float)(srcX + srcw) / info->accel_state->texW[0], (float)srcY / info->accel_state->texH[0], (float)(srcX + srcw) + 0.5, (float)srcY + 0.5); + } else { + VTX_OUT_FILTER((float)dstX, (float)dstY, + (float)srcX / info->accel_state->texW[0], (float)srcY / info->accel_state->texH[0], + (float)srcX + 0.5, (float)srcY + 0.5); + VTX_OUT_FILTER((float)dstX, (float)(dstY + dsth * 2), + (float)srcX / info->accel_state->texW[0], (float)(srcY + srch * 2) / info->accel_state->texH[0], + (float)srcX + 0.5, (float)(srcY + srch * 2) + 0.5); + VTX_OUT_FILTER((float)(dstX + dstw * 2), (float)dstY, + (float)(srcX + srcw * 2) / info->accel_state->texW[0], (float)srcY / info->accel_state->texH[0], + (float)(srcX + srcw * 2) + 0.5, (float)srcY + 0.5); + } } else { - if (IS_R300_3D || IS_R500_3D) { - VTX_OUT((float)dstX, (float)dstY, - (float)srcX / info->accel_state->texW[0], (float)srcY / info->accel_state->texH[0]); - VTX_OUT((float)dstX, (float)(dstY + dsth), - (float)srcX / info->accel_state->texW[0], (float)(srcY + srch) / info->accel_state->texH[0]); - VTX_OUT((float)(dstX + dstw), (float)(dstY + dsth), - (float)(srcX + srcw) / info->accel_state->texW[0], (float)(srcY + srch) / info->accel_state->texH[0]); - VTX_OUT((float)(dstX + dstw), (float)dstY, - (float)(srcX + srcw) / info->accel_state->texW[0], (float)srcY / info->accel_state->texH[0]); + if (IS_R300_3D || IS_R500_3D) { + if (use_quad) { + VTX_OUT((float)dstX, (float)dstY, + (float)srcX / info->accel_state->texW[0], (float)srcY / info->accel_state->texH[0]); + VTX_OUT((float)dstX, (float)(dstY + dsth), + (float)srcX / info->accel_state->texW[0], (float)(srcY + srch) / info->accel_state->texH[0]); + VTX_OUT((float)(dstX + dstw), (float)(dstY + dsth), + (float)(srcX + srcw) / info->accel_state->texW[0], (float)(srcY + srch) / info->accel_state->texH[0]); + VTX_OUT((float)(dstX + dstw), (float)dstY, + (float)(srcX + srcw) / info->accel_state->texW[0], (float)srcY / info->accel_state->texH[0]); } else { - /* - * Just render a rect (using three coords). - */ - VTX_OUT((float)dstX, (float)(dstY + dsth), - (float)srcX / info->accel_state->texW[0], (float)(srcY + srch) / info->accel_state->texH[0]); - VTX_OUT((float)(dstX + dstw), (float)(dstY + dsth), - (float)(srcX + srcw) / info->accel_state->texW[0], (float)(srcY + srch) / info->accel_state->texH[0]); - VTX_OUT((float)(dstX + dstw), (float)dstY, - (float)(srcX + srcw) / info->accel_state->texW[0], (float)srcY / info->accel_state->texH[0]); + /* + * Render a big, scissored triangle. This means + * doubling the triangle size and adjusting + * texture coordinates. + */ + VTX_OUT((float)dstX, (float)dstY, + (float)srcX / info->accel_state->texW[0], (float)srcY / info->accel_state->texH[0]); + VTX_OUT((float)dstX, (float)(dstY + dsth * 2), + (float)srcX / info->accel_state->texW[0], (float)(srcY + srch * 2) / info->accel_state->texH[0]); + VTX_OUT((float)(dstX + dstw * 2), (float)dstY, + (float)(srcX + srcw * 2) / info->accel_state->texW[0], (float)srcY / info->accel_state->texH[0]); } + } else { + /* + * Just render a rect (using three coords). + */ + VTX_OUT((float)dstX, (float)(dstY + dsth), + (float)srcX / info->accel_state->texW[0], (float)(srcY + srch) / info->accel_state->texH[0]); + VTX_OUT((float)(dstX + dstw), (float)(dstY + dsth), + (float)(srcX + srcw) / info->accel_state->texW[0], (float)(srcY + srch) / info->accel_state->texH[0]); + VTX_OUT((float)(dstX + dstw), (float)dstY, + (float)(srcX + srcw) / info->accel_state->texW[0], (float)srcY / info->accel_state->texH[0]); + } } if (IS_R300_3D || IS_R500_3D) commit 4e96278b581e296c1203d97a6d7aa3bff3977222 Author: Dave Airlie <[email protected]> Date: Mon Dec 22 15:58:35 2008 +1000 atombios/tv: add an option to enable atom tv-out for users. This code is still experimental but we will allow users to enable it for experimental reasons diff --git a/man/radeon.man b/man/radeon.man index f8526df..19ffb94 100644 --- a/man/radeon.man +++ b/man/radeon.man @@ -550,6 +550,12 @@ controller has passed the destination region. It reduces tearing at the cost of performance. The default is .B off. +.TP +.BI "Option \*qATOMTvOut\*q \*q" boolean \*q +This option enables experimental TV-out support for r500 and r600 atombios chips. +tv-out is experimental and may not function on these chips as well as hoped for. +The default is +.B off. .SH SEE ALSO __xservername__(__appmansuffix__), __xconfigfile__(__filemansuffix__), xorgconfig(__appmansuffix__), Xserver(__appmansuffix__), X(__miscmansuffix__) diff --git a/src/radeon.h b/src/radeon.h index 818ec4d..f7f9c09 100644 --- a/src/radeon.h +++ b/src/radeon.h @@ -205,7 +205,8 @@ typedef enum { OPTION_IGNORE_LID_STATUS, OPTION_DEFAULT_TVDAC_ADJ, OPTION_INT10, - OPTION_EXA_VSYNC + OPTION_EXA_VSYNC, + OPTION_ATOM_TVOUT } RADEONOpts; diff --git a/src/radeon_atombios.c b/src/radeon_atombios.c index c9c7ae2..3cd7eae 100644 --- a/src/radeon_atombios.c +++ b/src/radeon_atombios.c @@ -1572,6 +1572,10 @@ RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn) ATOM_CONNECTOR_OBJECT_TABLE *con_obj; ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj = NULL; int i, j; + Bool enable_tv = FALSE; + + if (xf86ReturnOptValBool(info->Options, OPTION_ATOM_TVOUT, FALSE)) + enable_tv = TRUE; atomDataPtr = info->atomBIOS->atomDataPtr; if (!rhdAtomGetTableRevisionAndSize((ATOM_COMMON_TABLE_HEADER *)(atomDataPtr->Object_Header), &crev, &frev, &size)) @@ -1702,7 +1706,10 @@ RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn) if (info->BiosConnector[i].ConnectorType == CONNECTOR_DIN || info->BiosConnector[i].ConnectorType == CONNECTOR_STV || info->BiosConnector[i].ConnectorType == CONNECTOR_CTV) - info->BiosConnector[i].devices |= (1 << ATOM_DEVICE_TV1_INDEX); + if (enable_tv) + info->BiosConnector[i].devices |= (1 << ATOM_DEVICE_TV1_INDEX); + else + info->BiosConnector[i].valid = FALSE; else info->BiosConnector[i].devices |= (1 << ATOM_DEVICE_CRT1_INDEX); info->BiosConnector[i].DACType = DAC_PRIMARY; @@ -1715,7 +1722,10 @@ RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn) if (info->BiosConnector[i].ConnectorType == CONNECTOR_DIN || info->BiosConnector[i].ConnectorType == CONNECTOR_STV || info->BiosConnector[i].ConnectorType == CONNECTOR_CTV) - info->BiosConnector[i].devices |= (1 << ATOM_DEVICE_TV1_INDEX); + if (enable_tv) + info->BiosConnector[i].devices |= (1 << ATOM_DEVICE_TV1_INDEX); + else + info->BiosConnector[i].valid = FALSE; else info->BiosConnector[i].devices |= (1 << ATOM_DEVICE_CRT2_INDEX); info->BiosConnector[i].DACType = DAC_TVDAC; @@ -1978,6 +1988,10 @@ RADEONGetATOMConnectorInfoFromBIOSConnectorTable (ScrnInfoPtr pScrn) atomDataTablesPtr atomDataPtr; uint8_t crev, frev; int i, j; + Bool enable_tv = FALSE; + + if (xf86ReturnOptValBool(info->Options, OPTION_ATOM_TVOUT, FALSE)) + enable_tv = TRUE; atomDataPtr = info->atomBIOS->atomDataPtr; @@ -1998,20 +2012,16 @@ RADEONGetATOMConnectorInfoFromBIOSConnectorTable (ScrnInfoPtr pScrn) continue; } -#if 1 - if (i == ATOM_DEVICE_CV_INDEX) { + if (!enable_tv && (i == ATOM_DEVICE_CV_INDEX)) { xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Skipping Component Video\n"); info->BiosConnector[i].valid = FALSE; continue; } -#endif -#if 1 - if (i == ATOM_DEVICE_TV1_INDEX) { + if (!enable_tv && (i == ATOM_DEVICE_TV1_INDEX)) { xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Skipping TV-Out\n"); info->BiosConnector[i].valid = FALSE; continue; } -#endif info->BiosConnector[i].valid = TRUE; info->BiosConnector[i].load_detection = TRUE; diff --git a/src/radeon_driver.c b/src/radeon_driver.c index d414854..e53edbb 100644 --- a/src/radeon_driver.c +++ b/src/radeon_driver.c @@ -192,6 +192,7 @@ static const OptionInfoRec RADEONOptions[] = { { OPTION_DEFAULT_TVDAC_ADJ, "DefaultTVDACAdj", OPTV_BOOLEAN, {0}, FALSE }, { OPTION_INT10, "Int10", OPTV_BOOLEAN, {0}, FALSE }, { OPTION_EXA_VSYNC, "EXAVSync", OPTV_BOOLEAN, {0}, FALSE }, + { OPTION_ATOM_TVOUT, "ATOMTVOut", OPTV_BOOLEAN, {0}, FALSE }, { -1, NULL, OPTV_NONE, {0}, FALSE } }; commit d52882d8188830dd52fa112dadcf5ea7f3e5fd5e Author: Dave Airlie <[email protected]> Date: Mon Dec 22 09:27:47 2008 +1000 radeon: setup 3D engine even when no DRI. This should fix some missing font issues in EXA without DRI cases. diff --git a/src/radeon.h b/src/radeon.h index a67962c..9f0e55a 100644 --- a/src/radeon.h +++ b/src/radeon.h @@ -1329,8 +1329,9 @@ do { \ case EXA_ENGINEMODE_3D: \ break; \ } \ - if (flush && info->directRenderingEnabled) { \ - RADEONCPFlushIndirect(pScrn, 1); \ + if (flush) { \ + if (info->directRenderingEnabled) \ + RADEONCPFlushIndirect(pScrn, 1); \ RADEONInit3DEngine(pScrn); \ } \ info->accel_state->engineMode = EXA_ENGINEMODE_3D; \ commit 2346fd7cbd90dcdce2b361d374a53da064fa6a12 Author: Dave Airlie <[email protected]> Date: Thu Dec 18 16:35:13 2008 +1000 radeon: add all new pci ids for rv730/rv710 families diff --git a/src/ati_pciids_gen.h b/src/ati_pciids_gen.h index 7819cf6..6f23628 100644 --- a/src/ati_pciids_gen.h +++ b/src/ati_pciids_gen.h @@ -334,8 +334,23 @@ #define PCI_CHIP_RV770_9440 0x9440 #define PCI_CHIP_RV770_9441 0x9441 #define PCI_CHIP_RV770_9442 0x9442 +#define PCI_CHIP_RV770_9444 0x9444 +#define PCI_CHIP_RV770_9446 0x9446 +#define PCI_CHIP_RV770_944A 0x944A +#define PCI_CHIP_RV770_944B 0x944B +#define PCI_CHIP_RV770_944C 0x944C +#define PCI_CHIP_RV770_944E 0x944E +#define PCI_CHIP_RV770_9450 0x9450 +#define PCI_CHIP_RV770_9452 0x9452 +#define PCI_CHIP_RV770_9456 0x9456 +#define PCI_CHIP_RV770_945A 0x945A +#define PCI_CHIP_RV770_945B 0x945B +#define PCI_CHIP_RV730_9487 0x9487 +#define PCI_CHIP_RV730_948F 0x948F #define PCI_CHIP_RV730_9490 0x9490 #define PCI_CHIP_RV730_9498 0x9498 +#define PCI_CHIP_RV730_949C 0x949C +#define PCI_CHIP_RV730_949E 0x949E #define PCI_CHIP_RV730_949F 0x949F #define PCI_CHIP_RV610_94C0 0x94C0 #define PCI_CHIP_RV610_94C1 0x94C1 @@ -355,6 +370,12 @@ #define PCI_CHIP_RV670_950F 0x950F #define PCI_CHIP_RV670_9511 0x9511 #define PCI_CHIP_RV670_9515 0x9515 +#define PCI_CHIP_RV710_9540 0x9540 +#define PCI_CHIP_RV710_9541 0x9541 +#define PCI_CHIP_RV710_954E 0x954E +#define PCI_CHIP_RV710_954F 0x954F +#define PCI_CHIP_RV710_9552 0x9552 +#define PCI_CHIP_RV710_9553 0x9553 #define PCI_CHIP_RV630_9580 0x9580 #define PCI_CHIP_RV630_9581 0x9581 #define PCI_CHIP_RV630_9583 0x9583 @@ -367,11 +388,12 @@ #define PCI_CHIP_RV630_958C 0x958C #define PCI_CHIP_RV630_958D 0x958D #define PCI_CHIP_RV630_958E 0x958E +#define PCI_CHIP_RV710_9592 0x9592 #define PCI_CHIP_RV620_95C0 0x95C0 -#define PCI_CHIP_RV620_95C5 0x95C5 -#define PCI_CHIP_RV620_95C7 0x95C7 #define PCI_CHIP_RV620_95C2 0x95C2 #define PCI_CHIP_RV620_95C4 0x95C4 +#define PCI_CHIP_RV620_95C5 0x95C5 +#define PCI_CHIP_RV620_95C7 0x95C7 #define PCI_CHIP_RV620_95CD 0x95CD #define PCI_CHIP_RV620_95CE 0x95CE #define PCI_CHIP_RV620_95CF 0x95CF diff --git a/src/pcidb/ati_pciids.csv b/src/pcidb/ati_pciids.csv index ff9979f..aea0931 100644 --- a/src/pcidb/ati_pciids.csv +++ b/src/pcidb/ati_pciids.csv @@ -335,9 +335,24 @@ "0x9440","RV770_9440","RV770",,,,,,"ATI Radeon 4800 Series" "0x9441","RV770_9441","RV770",,,,,,"ATI Radeon HD 4870 x2" "0x9442","RV770_9442","RV770",,,,,,"ATI Radeon 4800 Series" +"0x9444","RV770_9444","RV770",,,,,,"ATI FirePro V8750 (FireGL)" +"0x9446","RV770_9446","RV770",,,,,,"ATI FirePro V7760 (FireGL)" +"0x944A","RV770_944A","RV770",1,,,,,"ATI Mobility RADEON HD 4850" +"0x944B","RV770_944B","RV770",1,,,,,"ATI Mobility RADEON HD 4850 X2" +"0x944C","RV770_944C","RV770",,,,,,"ATI Radeon 4800 Series" +"0x944E","RV770_944E","RV770",,,,,,"ATI FirePro RV770" +"0x9450","RV770_9450","RV770",,,,,,"AMD FireStream 9270" +"0x9452","RV770_9452","RV770",,,,,,"AMD FireStream 9250" +"0x9456","RV770_9456","RV770",,,,,,"ATI FirePro V8700 (FireGL)" +"0x945A","RV770_945A","RV770",1,,,,,"ATI Mobility RADEON HD 4870" +"0x945B","RV770_945B","RV770",1,,,,,"ATI Mobility RADEON M98" +"0x9487","RV730_9487","RV730",,,,,,"ATI Radeon RV730 (AGP)" +"0x948F","RV730_948F","RV730",,,,,,"ATI Radeon RV730 (AGP)" "0x9490","RV730_9490","RV730",,,,,,"ATI RV730XT [Radeon HD 4670]" "0x9498","RV730_9498","RV730",,,,,,"ATI RV730 PRO [Radeon HD 4650]" -"0x949F","RV730_949F","RV730",,,,,,"ATI RV730 [FirePro V5700]" +"0x949C","RV730_949C","RV730",,,,,,"ATI FirePro V7750 (FireGL)" +"0x949E","RV730_949E","RV730",,,,,,"ATI FirePro V5700 (FireGL)" +"0x949F","RV730_949F","RV730",,,,,,"ATI FirePro V3750 (FireGL)" "0x94C0","RV610_94C0","RV610",,,,,,"ATI RV610" "0x94C1","RV610_94C1","RV610",,,,,,"ATI Radeon HD 2400 XT" "0x94C3","RV610_94C3","RV610",,,,,,"ATI Radeon HD 2400 Pro" @@ -356,6 +371,12 @@ "0x950F","RV670_950F","RV670",,,,,,"ATI Radeon HD3870 X2" "0x9511","RV670_9511","RV670",,,,,,"ATI FireGL V7700" "0x9515","RV670_9515","RV670",,,,,,"ATI Radeon HD3850" +"0x9540","RV710_9540","RV710",,,,,,"ATI Radeon HD 4550" +"0x9541","RV710_9541","RV710",,,,,,"ATI Radeon RV710" +"0x954E","RV710_954E","RV710",,,,,,"ATI Radeon RV710" +"0x954F","RV710_954F","RV710",,,,,,"ATI Radeon HD 4350" +"0x9552","RV710_9552","RV710",1,,,,,"ATI Mobility Radeon 4300 Series" +"0x9553","RV710_9553","RV710",1,,,,,"ATI Mobility Radeon 4500 Series" "0x9580","RV630_9580","RV630",,,,,,"ATI RV630" "0x9581","RV630_9581","RV630",1,,,,,"ATI Mobility Radeon HD 2600" "0x9583","RV630_9583","RV630",1,,,,,"ATI Mobility Radeon HD 2600 XT" @@ -368,11 +389,12 @@ "0x958C","RV630_958C","RV630",,,,,,"ATI FireGL V5600" "0x958D","RV630_958D","RV630",,,,,,"ATI FireGL V3600" "0x958E","RV630_958E","RV630",,,,,,"ATI Radeon HD 2600 LE" +"0x9592","RV710_9592","RV710",,,,,,"ATI Radeon RV710" "0x95C0","RV620_95C0","RV620",,,,,,"ATI Radeon HD 3470" -"0x95C5","RV620_95C5","RV620",,,,,,"ATI Radeon HD 3450" -"0x95C7","RV620_95C7","RV620",,,,,,"ATI Radeon HD 3430" "0x95C2","RV620_95C2","RV620",1,,,,,"ATI Mobility Radeon HD 3430" "0x95C4","RV620_95C4","RV620",1,,,,,"ATI Mobility Radeon HD 3400 Series" +"0x95C5","RV620_95C5","RV620",,,,,,"ATI Radeon HD 3450" +"0x95C7","RV620_95C7","RV620",,,,,,"ATI Radeon HD 3430" "0x95CD","RV620_95CD","RV620",,,,,,"ATI FireMV 2450" "0x95CE","RV620_95CE","RV620",,,,,,"ATI FireMV 2260" "0x95CF","RV620_95CF","RV620",,,,,,"ATI FireMV 2260" diff --git a/src/radeon.h b/src/radeon.h index 818ec4d..a67962c 100644 --- a/src/radeon.h +++ b/src/radeon.h @@ -325,6 +325,7 @@ typedef enum { CHIP_FAMILY_RS780, CHIP_FAMILY_RV770, CHIP_FAMILY_RV730, + CHIP_FAMILY_RV710, CHIP_FAMILY_LAST } RADEONChipFamily; diff --git a/src/radeon_chipinfo_gen.h b/src/radeon_chipinfo_gen.h index a321fa1..627520b 100644 --- a/src/radeon_chipinfo_gen.h +++ b/src/radeon_chipinfo_gen.h @@ -254,8 +254,23 @@ RADEONCardInfo RADEONCards[] = { { 0x9440, CHIP_FAMILY_RV770, 0, 0, 0, 0, 0 }, { 0x9441, CHIP_FAMILY_RV770, 0, 0, 0, 0, 0 }, { 0x9442, CHIP_FAMILY_RV770, 0, 0, 0, 0, 0 }, + { 0x9444, CHIP_FAMILY_RV770, 0, 0, 0, 0, 0 }, + { 0x9446, CHIP_FAMILY_RV770, 0, 0, 0, 0, 0 }, + { 0x944A, CHIP_FAMILY_RV770, 1, 0, 0, 0, 0 }, + { 0x944B, CHIP_FAMILY_RV770, 1, 0, 0, 0, 0 }, + { 0x944C, CHIP_FAMILY_RV770, 0, 0, 0, 0, 0 }, + { 0x944E, CHIP_FAMILY_RV770, 0, 0, 0, 0, 0 }, + { 0x9450, CHIP_FAMILY_RV770, 0, 0, 0, 0, 0 }, + { 0x9452, CHIP_FAMILY_RV770, 0, 0, 0, 0, 0 }, + { 0x9456, CHIP_FAMILY_RV770, 0, 0, 0, 0, 0 }, + { 0x945A, CHIP_FAMILY_RV770, 1, 0, 0, 0, 0 }, + { 0x945B, CHIP_FAMILY_RV770, 1, 0, 0, 0, 0 }, + { 0x9487, CHIP_FAMILY_RV730, 0, 0, 0, 0, 0 }, + { 0x948F, CHIP_FAMILY_RV730, 0, 0, 0, 0, 0 }, { 0x9490, CHIP_FAMILY_RV730, 0, 0, 0, 0, 0 }, { 0x9498, CHIP_FAMILY_RV730, 0, 0, 0, 0, 0 }, + { 0x949C, CHIP_FAMILY_RV730, 0, 0, 0, 0, 0 }, + { 0x949E, CHIP_FAMILY_RV730, 0, 0, 0, 0, 0 }, { 0x949F, CHIP_FAMILY_RV730, 0, 0, 0, 0, 0 }, { 0x94C0, CHIP_FAMILY_RV610, 0, 0, 0, 0, 0 }, { 0x94C1, CHIP_FAMILY_RV610, 0, 0, 0, 0, 0 }, @@ -275,6 +290,12 @@ RADEONCardInfo RADEONCards[] = { { 0x950F, CHIP_FAMILY_RV670, 0, 0, 0, 0, 0 }, { 0x9511, CHIP_FAMILY_RV670, 0, 0, 0, 0, 0 }, { 0x9515, CHIP_FAMILY_RV670, 0, 0, 0, 0, 0 }, + { 0x9540, CHIP_FAMILY_RV710, 0, 0, 0, 0, 0 }, + { 0x9541, CHIP_FAMILY_RV710, 0, 0, 0, 0, 0 }, + { 0x954E, CHIP_FAMILY_RV710, 0, 0, 0, 0, 0 }, + { 0x954F, CHIP_FAMILY_RV710, 0, 0, 0, 0, 0 }, + { 0x9552, CHIP_FAMILY_RV710, 1, 0, 0, 0, 0 }, + { 0x9553, CHIP_FAMILY_RV710, 1, 0, 0, 0, 0 }, { 0x9580, CHIP_FAMILY_RV630, 0, 0, 0, 0, 0 }, { 0x9581, CHIP_FAMILY_RV630, 1, 0, 0, 0, 0 }, { 0x9583, CHIP_FAMILY_RV630, 1, 0, 0, 0, 0 }, @@ -287,11 +308,12 @@ RADEONCardInfo RADEONCards[] = { { 0x958C, CHIP_FAMILY_RV630, 0, 0, 0, 0, 0 }, { 0x958D, CHIP_FAMILY_RV630, 0, 0, 0, 0, 0 }, { 0x958E, CHIP_FAMILY_RV630, 0, 0, 0, 0, 0 }, + { 0x9592, CHIP_FAMILY_RV710, 0, 0, 0, 0, 0 }, { 0x95C0, CHIP_FAMILY_RV620, 0, 0, 0, 0, 0 }, - { 0x95C5, CHIP_FAMILY_RV620, 0, 0, 0, 0, 0 }, - { 0x95C7, CHIP_FAMILY_RV620, 0, 0, 0, 0, 0 }, { 0x95C2, CHIP_FAMILY_RV620, 1, 0, 0, 0, 0 }, { 0x95C4, CHIP_FAMILY_RV620, 1, 0, 0, 0, 0 }, + { 0x95C5, CHIP_FAMILY_RV620, 0, 0, 0, 0, 0 }, + { 0x95C7, CHIP_FAMILY_RV620, 0, 0, 0, 0, 0 }, { 0x95CD, CHIP_FAMILY_RV620, 0, 0, 0, 0, 0 }, { 0x95CE, CHIP_FAMILY_RV620, 0, 0, 0, 0, 0 }, { 0x95CF, CHIP_FAMILY_RV620, 0, 0, 0, 0, 0 }, diff --git a/src/radeon_chipset_gen.h b/src/radeon_chipset_gen.h index 03328e5..b8a8a65 100644 --- a/src/radeon_chipset_gen.h +++ b/src/radeon_chipset_gen.h @@ -254,9 +254,24 @@ static SymTabRec RADEONChipsets[] = { { PCI_CHIP_RV770_9440, "ATI Radeon 4800 Series" }, { PCI_CHIP_RV770_9441, "ATI Radeon HD 4870 x2" }, { PCI_CHIP_RV770_9442, "ATI Radeon 4800 Series" }, + { PCI_CHIP_RV770_9444, "ATI FirePro V8750 (FireGL)" }, + { PCI_CHIP_RV770_9446, "ATI FirePro V7760 (FireGL)" }, + { PCI_CHIP_RV770_944A, "ATI Mobility RADEON HD 4850" }, + { PCI_CHIP_RV770_944B, "ATI Mobility RADEON HD 4850 X2" }, + { PCI_CHIP_RV770_944C, "ATI Radeon 4800 Series" }, + { PCI_CHIP_RV770_944E, "ATI FirePro RV770" }, + { PCI_CHIP_RV770_9450, "AMD FireStream 9270" }, + { PCI_CHIP_RV770_9452, "AMD FireStream 9250" }, + { PCI_CHIP_RV770_9456, "ATI FirePro V8700 (FireGL)" }, + { PCI_CHIP_RV770_945A, "ATI Mobility RADEON HD 4870" }, + { PCI_CHIP_RV770_945B, "ATI Mobility RADEON M98" }, + { PCI_CHIP_RV730_9487, "ATI Radeon RV730 (AGP)" }, + { PCI_CHIP_RV730_948F, "ATI Radeon RV730 (AGP)" }, { PCI_CHIP_RV730_9490, "ATI RV730XT [Radeon HD 4670]" }, { PCI_CHIP_RV730_9498, "ATI RV730 PRO [Radeon HD 4650]" }, - { PCI_CHIP_RV730_949F, "ATI RV730 [FirePro V5700]" }, + { PCI_CHIP_RV730_949C, "ATI FirePro V7750 (FireGL)" }, + { PCI_CHIP_RV730_949E, "ATI FirePro V5700 (FireGL)" }, + { PCI_CHIP_RV730_949F, "ATI FirePro V3750 (FireGL)" }, { PCI_CHIP_RV610_94C0, "ATI RV610" }, { PCI_CHIP_RV610_94C1, "ATI Radeon HD 2400 XT" }, { PCI_CHIP_RV610_94C3, "ATI Radeon HD 2400 Pro" }, @@ -275,6 +290,12 @@ static SymTabRec RADEONChipsets[] = { { PCI_CHIP_RV670_950F, "ATI Radeon HD3870 X2" }, { PCI_CHIP_RV670_9511, "ATI FireGL V7700" }, { PCI_CHIP_RV670_9515, "ATI Radeon HD3850" }, + { PCI_CHIP_RV710_9540, "ATI Radeon HD 4550" }, + { PCI_CHIP_RV710_9541, "ATI Radeon RV710" }, + { PCI_CHIP_RV710_954E, "ATI Radeon RV710" }, + { PCI_CHIP_RV710_954F, "ATI Radeon HD 4350" }, + { PCI_CHIP_RV710_9552, "ATI Mobility Radeon 4300 Series" }, + { PCI_CHIP_RV710_9553, "ATI Mobility Radeon 4500 Series" }, { PCI_CHIP_RV630_9580, "ATI RV630" }, { PCI_CHIP_RV630_9581, "ATI Mobility Radeon HD 2600" }, { PCI_CHIP_RV630_9583, "ATI Mobility Radeon HD 2600 XT" }, @@ -287,11 +308,12 @@ static SymTabRec RADEONChipsets[] = { { PCI_CHIP_RV630_958C, "ATI FireGL V5600" }, { PCI_CHIP_RV630_958D, "ATI FireGL V3600" }, { PCI_CHIP_RV630_958E, "ATI Radeon HD 2600 LE" }, + { PCI_CHIP_RV710_9592, "ATI Radeon RV710" }, { PCI_CHIP_RV620_95C0, "ATI Radeon HD 3470" }, - { PCI_CHIP_RV620_95C5, "ATI Radeon HD 3450" }, - { PCI_CHIP_RV620_95C7, "ATI Radeon HD 3430" }, { PCI_CHIP_RV620_95C2, "ATI Mobility Radeon HD 3430" }, { PCI_CHIP_RV620_95C4, "ATI Mobility Radeon HD 3400 Series" }, + { PCI_CHIP_RV620_95C5, "ATI Radeon HD 3450" }, + { PCI_CHIP_RV620_95C7, "ATI Radeon HD 3430" }, { PCI_CHIP_RV620_95CD, "ATI FireMV 2450" }, { PCI_CHIP_RV620_95CE, "ATI FireMV 2260" }, { PCI_CHIP_RV620_95CF, "ATI FireMV 2260" }, diff --git a/src/radeon_pci_chipset_gen.h b/src/radeon_pci_chipset_gen.h index 1e97289..525eafa 100644 --- a/src/radeon_pci_chipset_gen.h +++ b/src/radeon_pci_chipset_gen.h @@ -254,8 +254,23 @@ PciChipsets RADEONPciChipsets[] = { { PCI_CHIP_RV770_9440, PCI_CHIP_RV770_9440, RES_SHARED_VGA }, { PCI_CHIP_RV770_9441, PCI_CHIP_RV770_9441, RES_SHARED_VGA }, { PCI_CHIP_RV770_9442, PCI_CHIP_RV770_9442, RES_SHARED_VGA }, + { PCI_CHIP_RV770_9444, PCI_CHIP_RV770_9444, RES_SHARED_VGA }, + { PCI_CHIP_RV770_9446, PCI_CHIP_RV770_9446, RES_SHARED_VGA }, + { PCI_CHIP_RV770_944A, PCI_CHIP_RV770_944A, RES_SHARED_VGA }, + { PCI_CHIP_RV770_944B, PCI_CHIP_RV770_944B, RES_SHARED_VGA }, + { PCI_CHIP_RV770_944C, PCI_CHIP_RV770_944C, RES_SHARED_VGA }, + { PCI_CHIP_RV770_944E, PCI_CHIP_RV770_944E, RES_SHARED_VGA }, + { PCI_CHIP_RV770_9450, PCI_CHIP_RV770_9450, RES_SHARED_VGA }, + { PCI_CHIP_RV770_9452, PCI_CHIP_RV770_9452, RES_SHARED_VGA }, + { PCI_CHIP_RV770_9456, PCI_CHIP_RV770_9456, RES_SHARED_VGA }, + { PCI_CHIP_RV770_945A, PCI_CHIP_RV770_945A, RES_SHARED_VGA }, + { PCI_CHIP_RV770_945B, PCI_CHIP_RV770_945B, RES_SHARED_VGA }, + { PCI_CHIP_RV730_9487, PCI_CHIP_RV730_9487, RES_SHARED_VGA }, + { PCI_CHIP_RV730_948F, PCI_CHIP_RV730_948F, RES_SHARED_VGA }, { PCI_CHIP_RV730_9490, PCI_CHIP_RV730_9490, RES_SHARED_VGA }, { PCI_CHIP_RV730_9498, PCI_CHIP_RV730_9498, RES_SHARED_VGA }, + { PCI_CHIP_RV730_949C, PCI_CHIP_RV730_949C, RES_SHARED_VGA }, + { PCI_CHIP_RV730_949E, PCI_CHIP_RV730_949E, RES_SHARED_VGA }, { PCI_CHIP_RV730_949F, PCI_CHIP_RV730_949F, RES_SHARED_VGA }, { PCI_CHIP_RV610_94C0, PCI_CHIP_RV610_94C0, RES_SHARED_VGA }, { PCI_CHIP_RV610_94C1, PCI_CHIP_RV610_94C1, RES_SHARED_VGA }, @@ -275,6 +290,12 @@ PciChipsets RADEONPciChipsets[] = { { PCI_CHIP_RV670_950F, PCI_CHIP_RV670_950F, RES_SHARED_VGA }, { PCI_CHIP_RV670_9511, PCI_CHIP_RV670_9511, RES_SHARED_VGA }, { PCI_CHIP_RV670_9515, PCI_CHIP_RV670_9515, RES_SHARED_VGA }, + { PCI_CHIP_RV710_9540, PCI_CHIP_RV710_9540, RES_SHARED_VGA }, + { PCI_CHIP_RV710_9541, PCI_CHIP_RV710_9541, RES_SHARED_VGA }, + { PCI_CHIP_RV710_954E, PCI_CHIP_RV710_954E, RES_SHARED_VGA }, + { PCI_CHIP_RV710_954F, PCI_CHIP_RV710_954F, RES_SHARED_VGA }, + { PCI_CHIP_RV710_9552, PCI_CHIP_RV710_9552, RES_SHARED_VGA }, + { PCI_CHIP_RV710_9553, PCI_CHIP_RV710_9553, RES_SHARED_VGA }, { PCI_CHIP_RV630_9580, PCI_CHIP_RV630_9580, RES_SHARED_VGA }, { PCI_CHIP_RV630_9581, PCI_CHIP_RV630_9581, RES_SHARED_VGA }, { PCI_CHIP_RV630_9583, PCI_CHIP_RV630_9583, RES_SHARED_VGA }, @@ -287,11 +308,12 @@ PciChipsets RADEONPciChipsets[] = { { PCI_CHIP_RV630_958C, PCI_CHIP_RV630_958C, RES_SHARED_VGA }, { PCI_CHIP_RV630_958D, PCI_CHIP_RV630_958D, RES_SHARED_VGA }, { PCI_CHIP_RV630_958E, PCI_CHIP_RV630_958E, RES_SHARED_VGA }, + { PCI_CHIP_RV710_9592, PCI_CHIP_RV710_9592, RES_SHARED_VGA }, { PCI_CHIP_RV620_95C0, PCI_CHIP_RV620_95C0, RES_SHARED_VGA }, - { PCI_CHIP_RV620_95C5, PCI_CHIP_RV620_95C5, RES_SHARED_VGA }, - { PCI_CHIP_RV620_95C7, PCI_CHIP_RV620_95C7, RES_SHARED_VGA }, { PCI_CHIP_RV620_95C2, PCI_CHIP_RV620_95C2, RES_SHARED_VGA }, { PCI_CHIP_RV620_95C4, PCI_CHIP_RV620_95C4, RES_SHARED_VGA }, + { PCI_CHIP_RV620_95C5, PCI_CHIP_RV620_95C5, RES_SHARED_VGA }, + { PCI_CHIP_RV620_95C7, PCI_CHIP_RV620_95C7, RES_SHARED_VGA }, { PCI_CHIP_RV620_95CD, PCI_CHIP_RV620_95CD, RES_SHARED_VGA }, { PCI_CHIP_RV620_95CE, PCI_CHIP_RV620_95CE, RES_SHARED_VGA }, { PCI_CHIP_RV620_95CF, PCI_CHIP_RV620_95CF, RES_SHARED_VGA }, diff --git a/src/radeon_pci_device_match_gen.h b/src/radeon_pci_device_match_gen.h index e05697b..878fe56 100644 --- a/src/radeon_pci_device_match_gen.h +++ b/src/radeon_pci_device_match_gen.h @@ -254,8 +254,23 @@ static const struct pci_id_match radeon_device_match[] = { ATI_DEVICE_MATCH( PCI_CHIP_RV770_9440, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV770_9441, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV770_9442, 0 ), + ATI_DEVICE_MATCH( PCI_CHIP_RV770_9444, 0 ), + ATI_DEVICE_MATCH( PCI_CHIP_RV770_9446, 0 ), + ATI_DEVICE_MATCH( PCI_CHIP_RV770_944A, 0 ), + ATI_DEVICE_MATCH( PCI_CHIP_RV770_944B, 0 ), + ATI_DEVICE_MATCH( PCI_CHIP_RV770_944C, 0 ), + ATI_DEVICE_MATCH( PCI_CHIP_RV770_944E, 0 ), + ATI_DEVICE_MATCH( PCI_CHIP_RV770_9450, 0 ), + ATI_DEVICE_MATCH( PCI_CHIP_RV770_9452, 0 ), + ATI_DEVICE_MATCH( PCI_CHIP_RV770_9456, 0 ), + ATI_DEVICE_MATCH( PCI_CHIP_RV770_945A, 0 ), + ATI_DEVICE_MATCH( PCI_CHIP_RV770_945B, 0 ), + ATI_DEVICE_MATCH( PCI_CHIP_RV730_9487, 0 ), + ATI_DEVICE_MATCH( PCI_CHIP_RV730_948F, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV730_9490, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV730_9498, 0 ), + ATI_DEVICE_MATCH( PCI_CHIP_RV730_949C, 0 ), + ATI_DEVICE_MATCH( PCI_CHIP_RV730_949E, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV730_949F, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV610_94C0, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV610_94C1, 0 ), @@ -275,6 +290,12 @@ static const struct pci_id_match radeon_device_match[] = { ATI_DEVICE_MATCH( PCI_CHIP_RV670_950F, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV670_9511, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV670_9515, 0 ), + ATI_DEVICE_MATCH( PCI_CHIP_RV710_9540, 0 ), + ATI_DEVICE_MATCH( PCI_CHIP_RV710_9541, 0 ), + ATI_DEVICE_MATCH( PCI_CHIP_RV710_954E, 0 ), + ATI_DEVICE_MATCH( PCI_CHIP_RV710_954F, 0 ), + ATI_DEVICE_MATCH( PCI_CHIP_RV710_9552, 0 ), + ATI_DEVICE_MATCH( PCI_CHIP_RV710_9553, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV630_9580, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV630_9581, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV630_9583, 0 ), @@ -287,11 +308,12 @@ static const struct pci_id_match radeon_device_match[] = { ATI_DEVICE_MATCH( PCI_CHIP_RV630_958C, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV630_958D, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV630_958E, 0 ), + ATI_DEVICE_MATCH( PCI_CHIP_RV710_9592, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV620_95C0, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV620_95C5, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV620_95C7, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV620_95C2, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV620_95C4, 0 ), + ATI_DEVICE_MATCH( PCI_CHIP_RV620_95C5, 0 ), + ATI_DEVICE_MATCH( PCI_CHIP_RV620_95C7, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV620_95CD, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV620_95CE, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV620_95CF, 0 ), commit b2b43905a5385a8bb0b59b8e50952863d8dacb59 Author: Alex Deucher <[email protected]> Date: Wed Dec 17 00:59:52 2008 -0500 -- To UNSUBSCRIBE, email to [email protected] with a subject of "unsubscribe". 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