configure.ac | 28 libdrm/Makefile.am | 6 libdrm/intel/Makefile.am | 1 libdrm/intel/intel_atomic.h | 61 + libdrm/intel/intel_bufmgr.c | 174 +- libdrm/intel/intel_bufmgr.h | 124 +- libdrm/intel/intel_bufmgr_fake.c | 2316 ++++++++++++++++++++------------------- libdrm/intel/intel_bufmgr_gem.c | 2176 ++++++++++++++++++++---------------- libdrm/intel/intel_bufmgr_priv.h | 378 +++--- libdrm/intel/mm.c | 414 +++--- libdrm/intel/mm.h | 16 libdrm/radeon/radeon_bo_gem.c | 8 shared-core/i915_drm.h | 16 shared-core/radeon_drm.h | 11 tests/Makefile.am | 23 15 files changed, 3109 insertions(+), 2643 deletions(-)
New commits: commit a107e5b12960f64722bff424502a4fc0ad33dc8f Author: Eric Anholt <[email protected]> Date: Thu Oct 8 16:59:17 2009 -0700 Bump to 2.4.15 for release. diff --git a/configure.ac b/configure.ac index 9832caf..870c056 100644 --- a/configure.ac +++ b/configure.ac @@ -19,7 +19,7 @@ # CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. AC_PREREQ(2.60) -AC_INIT([libdrm], 2.4.14, [[email protected]], libdrm) +AC_INIT([libdrm], 2.4.15, [[email protected]], libdrm) AC_USE_SYSTEM_EXTENSIONS AC_CONFIG_SRCDIR([Makefile.am]) AM_INIT_AUTOMAKE([dist-bzip2]) commit 9764061ab1b02e4b7bde1494b121604c5c4d4df8 Author: Eric Anholt <[email protected]> Date: Thu Oct 8 15:39:27 2009 -0700 intel: Remove the asserts about the ignored alignment parameter. I slipped it in with the alloc_tiled changes, since we were explicitly throwing the parameter away. It caught some bogus released code, which we've now fixed, so remove the asserts to keep old drivers working. diff --git a/libdrm/intel/intel_bufmgr_gem.c b/libdrm/intel/intel_bufmgr_gem.c index 3e46f53..b8be96d 100644 --- a/libdrm/intel/intel_bufmgr_gem.c +++ b/libdrm/intel/intel_bufmgr_gem.c @@ -545,7 +545,6 @@ drm_intel_gem_bo_alloc_for_render(drm_intel_bufmgr *bufmgr, unsigned long size, unsigned int alignment) { - assert(alignment <= 4096); return drm_intel_gem_bo_alloc_internal(bufmgr, name, size, BO_ALLOC_FOR_RENDER); } @@ -556,7 +555,6 @@ drm_intel_gem_bo_alloc(drm_intel_bufmgr *bufmgr, unsigned long size, unsigned int alignment) { - assert(alignment <= 4096); return drm_intel_gem_bo_alloc_internal(bufmgr, name, size, 0); } commit 3a7dfcdfafdd6ac83a4d3e7b4c1c52fd901b93ae Author: Jesse Barnes <[email protected]> Date: Tue Oct 6 14:34:06 2009 -0700 intel: Add a bo_alloc function for tiled BOs. This simplifies driver code in handling object allocation, and also gives us an opportunity to possibly cache tiled buffers if it turns out to be a win. [anholt: This is chopped out of the execbuf2 patch, as it seems to be useful separately and cleans up the execbuf2 changes to be more obvious] diff --git a/libdrm/intel/intel_bufmgr.c b/libdrm/intel/intel_bufmgr.c index fd5a2e7..2469cd8 100644 --- a/libdrm/intel/intel_bufmgr.c +++ b/libdrm/intel/intel_bufmgr.c @@ -58,6 +58,15 @@ drm_intel_bo *drm_intel_bo_alloc_for_render(drm_intel_bufmgr *bufmgr, return bufmgr->bo_alloc_for_render(bufmgr, name, size, alignment); } +drm_intel_bo * +drm_intel_bo_alloc_tiled(drm_intel_bufmgr *bufmgr, const char *name, + int x, int y, int cpp, uint32_t *tiling_mode, + unsigned long *pitch, unsigned long flags) +{ + return bufmgr->bo_alloc_tiled(bufmgr, name, x, y, cpp, + tiling_mode, pitch, flags); +} + void drm_intel_bo_reference(drm_intel_bo *bo) { bo->bufmgr->bo_reference(bo); diff --git a/libdrm/intel/intel_bufmgr.h b/libdrm/intel/intel_bufmgr.h index 0dbe880..3801ff3 100644 --- a/libdrm/intel/intel_bufmgr.h +++ b/libdrm/intel/intel_bufmgr.h @@ -77,12 +77,20 @@ struct _drm_intel_bo { int handle; }; +#define BO_ALLOC_FOR_RENDER (1<<0) + drm_intel_bo *drm_intel_bo_alloc(drm_intel_bufmgr *bufmgr, const char *name, unsigned long size, unsigned int alignment); drm_intel_bo *drm_intel_bo_alloc_for_render(drm_intel_bufmgr *bufmgr, const char *name, unsigned long size, unsigned int alignment); +drm_intel_bo *drm_intel_bo_alloc_tiled(drm_intel_bufmgr *bufmgr, + const char *name, + int x, int y, int cpp, + uint32_t *tiling_mode, + unsigned long *pitch, + unsigned long flags); void drm_intel_bo_reference(drm_intel_bo *bo); void drm_intel_bo_unreference(drm_intel_bo *bo); int drm_intel_bo_map(drm_intel_bo *bo, int write_enable); diff --git a/libdrm/intel/intel_bufmgr_fake.c b/libdrm/intel/intel_bufmgr_fake.c index f325482..54b3cb8 100644 --- a/libdrm/intel/intel_bufmgr_fake.c +++ b/libdrm/intel/intel_bufmgr_fake.c @@ -51,8 +51,6 @@ #include "mm.h" #include "libdrm_lists.h" -#define ALIGN(value, alignment) ((value + alignment - 1) & ~(alignment - 1)) - #define DBG(...) do { \ if (bufmgr_fake->bufmgr.debug) \ drmMsg(__VA_ARGS__); \ @@ -838,6 +836,32 @@ drm_intel_fake_bo_alloc(drm_intel_bufmgr *bufmgr, return &bo_fake->bo; } +static drm_intel_bo * +drm_intel_fake_bo_alloc_tiled(drm_intel_bufmgr * bufmgr, + const char *name, + int x, int y, int cpp, + uint32_t *tiling_mode, + unsigned long *pitch, + unsigned long flags) +{ + unsigned long stride, aligned_y; + + /* No runtime tiling support for fake. */ + *tiling_mode = I915_TILING_NONE; + + /* Align it for being a render target. Shouldn't need anything else. */ + stride = x * cpp; + stride = ROUND_UP_TO(stride, 64); + + /* 965 subspan loading alignment */ + aligned_y = ALIGN(y, 2); + + *pitch = stride; + + return drm_intel_fake_bo_alloc(bufmgr, name, stride * aligned_y, + 4096); +} + drm_intel_bo * drm_intel_bo_fake_alloc_static(drm_intel_bufmgr *bufmgr, const char *name, @@ -1565,6 +1589,7 @@ drm_intel_bufmgr *drm_intel_bufmgr_fake_init(int fd, /* Hook in methods */ bufmgr_fake->bufmgr.bo_alloc = drm_intel_fake_bo_alloc; bufmgr_fake->bufmgr.bo_alloc_for_render = drm_intel_fake_bo_alloc; + bufmgr_fake->bufmgr.bo_alloc_tiled = drm_intel_fake_bo_alloc_tiled; bufmgr_fake->bufmgr.bo_reference = drm_intel_fake_bo_reference; bufmgr_fake->bufmgr.bo_unreference = drm_intel_fake_bo_unreference; bufmgr_fake->bufmgr.bo_map = drm_intel_fake_bo_map; diff --git a/libdrm/intel/intel_bufmgr_gem.c b/libdrm/intel/intel_bufmgr_gem.c index aa55f2d..3e46f53 100644 --- a/libdrm/intel/intel_bufmgr_gem.c +++ b/libdrm/intel/intel_bufmgr_gem.c @@ -193,6 +193,66 @@ static void drm_intel_gem_bo_unreference(drm_intel_bo *bo); static void drm_intel_gem_bo_free(drm_intel_bo *bo); +static unsigned long +drm_intel_gem_bo_tile_size(drm_intel_bufmgr_gem *bufmgr_gem, unsigned long size, + uint32_t *tiling_mode) +{ + unsigned long min_size, max_size; + unsigned long i; + + if (*tiling_mode == I915_TILING_NONE) + return size; + + /* 965+ just need multiples of page size for tiling */ + if (IS_I965G(bufmgr_gem)) + return ROUND_UP_TO(size, 4096); + + /* Older chips need powers of two, of at least 512k or 1M */ + if (IS_I9XX(bufmgr_gem)) { + min_size = 1024*1024; + max_size = 128*1024*1024; + } else { + min_size = 512*1024; + max_size = 64*1024*1024; + } + + if (size > max_size) { + *tiling_mode = I915_TILING_NONE; + return size; + } + + for (i = min_size; i < size; i <<= 1) + ; + + return i; +} + +/* + * Round a given pitch up to the minimum required for X tiling on a + * given chip. We use 512 as the minimum to allow for a later tiling + * change. + */ +static unsigned long +drm_intel_gem_bo_tile_pitch(drm_intel_bufmgr_gem *bufmgr_gem, + unsigned long pitch, uint32_t tiling_mode) +{ + unsigned long tile_width = 512; + unsigned long i; + + if (tiling_mode == I915_TILING_NONE) + return ROUND_UP_TO(pitch, tile_width); + + /* 965 is flexible */ + if (IS_I965G(bufmgr_gem)) + return ROUND_UP_TO(pitch, tile_width); + + /* Pre-965 needs power of two tile width */ + for (i = tile_width; i < pitch; i <<= 1) + ; + + return i; +} + static struct drm_intel_gem_bo_bucket * drm_intel_gem_bo_bucket_for_size(drm_intel_bufmgr_gem *bufmgr_gem, unsigned long size) @@ -372,8 +432,7 @@ static drm_intel_bo * drm_intel_gem_bo_alloc_internal(drm_intel_bufmgr *bufmgr, const char *name, unsigned long size, - unsigned int alignment, - int for_render) + unsigned long flags) { drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr; drm_intel_bo_gem *bo_gem; @@ -382,6 +441,10 @@ drm_intel_gem_bo_alloc_internal(drm_intel_bufmgr *bufmgr, struct drm_intel_gem_bo_bucket *bucket; int alloc_from_cache; unsigned long bo_size; + int for_render = 0; + + if (flags & BO_ALLOC_FOR_RENDER) + for_render = 1; /* Round the allocated size up to a power of two number of pages. */ bucket = drm_intel_gem_bo_bucket_for_size(bufmgr_gem, size); @@ -482,8 +545,9 @@ drm_intel_gem_bo_alloc_for_render(drm_intel_bufmgr *bufmgr, unsigned long size, unsigned int alignment) { - return drm_intel_gem_bo_alloc_internal(bufmgr, name, size, alignment, - 1); + assert(alignment <= 4096); + return drm_intel_gem_bo_alloc_internal(bufmgr, name, size, + BO_ALLOC_FOR_RENDER); } static drm_intel_bo * @@ -492,8 +556,45 @@ drm_intel_gem_bo_alloc(drm_intel_bufmgr *bufmgr, unsigned long size, unsigned int alignment) { - return drm_intel_gem_bo_alloc_internal(bufmgr, name, size, alignment, - 0); + assert(alignment <= 4096); + return drm_intel_gem_bo_alloc_internal(bufmgr, name, size, 0); +} + +static drm_intel_bo * +drm_intel_gem_bo_alloc_tiled(drm_intel_bufmgr *bufmgr, const char *name, + int x, int y, int cpp, uint32_t *tiling_mode, + unsigned long *pitch, unsigned long flags) +{ + drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr; + drm_intel_bo *bo; + unsigned long size, stride, aligned_y = y; + int ret; + + if (*tiling_mode == I915_TILING_NONE) + aligned_y = ALIGN(y, 2); + else if (*tiling_mode == I915_TILING_X) + aligned_y = ALIGN(y, 8); + else if (*tiling_mode == I915_TILING_Y) + aligned_y = ALIGN(y, 32); + + stride = x * cpp; + stride = drm_intel_gem_bo_tile_pitch(bufmgr_gem, stride, *tiling_mode); + size = stride * aligned_y; + size = drm_intel_gem_bo_tile_size(bufmgr_gem, size, tiling_mode); + + bo = drm_intel_gem_bo_alloc_internal(bufmgr, name, size, flags); + if (!bo) + return NULL; + + ret = drm_intel_gem_bo_set_tiling(bo, tiling_mode, stride); + if (ret != 0) { + drm_intel_gem_bo_unreference(bo); + return NULL; + } + + *pitch = stride; + + return bo; } /** @@ -1565,6 +1666,7 @@ drm_intel_bufmgr_gem_init(int fd, int batch_size) bufmgr_gem->bufmgr.bo_alloc = drm_intel_gem_bo_alloc; bufmgr_gem->bufmgr.bo_alloc_for_render = drm_intel_gem_bo_alloc_for_render; + bufmgr_gem->bufmgr.bo_alloc_tiled = drm_intel_gem_bo_alloc_tiled; bufmgr_gem->bufmgr.bo_reference = drm_intel_gem_bo_reference; bufmgr_gem->bufmgr.bo_unreference = drm_intel_gem_bo_unreference; bufmgr_gem->bufmgr.bo_map = drm_intel_gem_bo_map; diff --git a/libdrm/intel/intel_bufmgr_priv.h b/libdrm/intel/intel_bufmgr_priv.h index 3b19eca..475c402 100644 --- a/libdrm/intel/intel_bufmgr_priv.h +++ b/libdrm/intel/intel_bufmgr_priv.h @@ -61,6 +61,28 @@ struct _drm_intel_bufmgr { unsigned long size, unsigned int alignment); + /** + * Allocate a tiled buffer object. + * + * Alignment for tiled objects is set automatically; the 'flags' + * argument provides a hint about how the object will be used initially. + * + * Valid tiling formats are: + * I915_TILING_NONE + * I915_TILING_X + * I915_TILING_Y + * + * Note the tiling format may be rejected; callers should check the + * 'tiling_mode' field on return, as well as the pitch value, which + * may have been rounded up to accommodate for tiling restrictions. + */ + drm_intel_bo *(*bo_alloc_tiled) (drm_intel_bufmgr *bufmgr, + const char *name, + int x, int y, int cpp, + uint32_t *tiling_mode, + unsigned long *pitch, + unsigned long flags); + /** Takes a reference on a buffer object */ void (*bo_reference) (drm_intel_bo *bo); @@ -225,4 +247,8 @@ struct _drm_intel_bufmgr { int debug; }; +#define ALIGN(value, alignment) ((value + alignment - 1) & ~(alignment - 1)) +#define ROUND_UP_TO(x, y) (((x) + (y) - 1) / (y) * (y)) +#define ROUND_UP_TO_MB(x) ROUND_UP_TO((x), 1024*1024) + #endif /* INTEL_BUFMGR_PRIV_H */ commit 02c775fc750b48ae25b6a4af51afbfe090ebada4 Author: Eric Anholt <[email protected]> Date: Tue Oct 6 15:25:21 2009 -0700 intel: Fix up some stale doxygen comments. diff --git a/libdrm/intel/intel_bufmgr.h b/libdrm/intel/intel_bufmgr.h index 9f07a94..0dbe880 100644 --- a/libdrm/intel/intel_bufmgr.h +++ b/libdrm/intel/intel_bufmgr.h @@ -56,8 +56,9 @@ struct _drm_intel_bo { unsigned long align; /** - * Card virtual address (offset from the beginning of the aperture) - * for the object. Only valid while validated. + * Last seen card virtual address (offset from the beginning of the + * aperture) for the object. This should be used to fill relocation + * entries when calling drm_intel_bo_emit_reloc() */ unsigned long offset; diff --git a/libdrm/intel/intel_bufmgr_priv.h b/libdrm/intel/intel_bufmgr_priv.h index b7cae6f..3b19eca 100644 --- a/libdrm/intel/intel_bufmgr_priv.h +++ b/libdrm/intel/intel_bufmgr_priv.h @@ -45,8 +45,7 @@ struct _drm_intel_bufmgr { * * Buffer objects are not necessarily initially mapped into CPU virtual * address space or graphics device aperture. They must be mapped - * using bo_map() to be used by the CPU, and validated for use using - * bo_validate() to be used from the graphics device. + * using bo_map() or drm_intel_gem_bo_map_gtt() to be used by the CPU. */ drm_intel_bo *(*bo_alloc) (drm_intel_bufmgr *bufmgr, const char *name, unsigned long size, unsigned int alignment); @@ -67,7 +66,7 @@ struct _drm_intel_bufmgr { /** * Releases a reference on a buffer object, freeing the data if - * rerefences remain. + * no references remain. */ void (*bo_unreference) (drm_intel_bo *bo); commit d70d60529f77ec73322be7b887fd6a3faf133bce Author: Eric Anholt <[email protected]> Date: Tue Oct 6 12:40:42 2009 -0700 intel: Reformat to the kernel coding style. Welcome to the 8-space future. This is done with: Lindent *.[ch] perl -pi -e 's|drm_intel_bo \* |drm_intel_bo *|g' *.[ch] perl -pi -e 's|drm_intel_bufmgr \* |drm_intel_bufmgr *|g' *.[ch] perl -pi -e 's|drm_intel_bo_gem \* |drm_intel_bo_gem *|g' *.[ch] perl -pi -e 's|drm_intel_bufmgr_gem \* |drm_intel_bufmgr_gem *|g' *.[ch] perl -pi -e 's|_fake \* |_fake *|g' *.[ch] hand-editing to whack indented comments into line and other touchups. diff --git a/libdrm/intel/intel_atomic.h b/libdrm/intel/intel_atomic.h index 562394a..9eb50a1 100644 --- a/libdrm/intel/intel_atomic.h +++ b/libdrm/intel/intel_atomic.h @@ -42,7 +42,9 @@ #define HAS_ATOMIC_OPS 1 -typedef struct { int atomic; } atomic_t; +typedef struct { + int atomic; +} atomic_t; # define atomic_read(x) ((x)->atomic) # define atomic_set(x, val) ((x)->atomic = (val)) diff --git a/libdrm/intel/intel_bufmgr.c b/libdrm/intel/intel_bufmgr.c index 20e59b8..fd5a2e7 100644 --- a/libdrm/intel/intel_bufmgr.c +++ b/libdrm/intel/intel_bufmgr.c @@ -44,124 +44,114 @@ * Convenience functions for buffer management methods. */ -drm_intel_bo * -drm_intel_bo_alloc(drm_intel_bufmgr *bufmgr, const char *name, - unsigned long size, unsigned int alignment) +drm_intel_bo *drm_intel_bo_alloc(drm_intel_bufmgr *bufmgr, const char *name, + unsigned long size, unsigned int alignment) { - return bufmgr->bo_alloc(bufmgr, name, size, alignment); + return bufmgr->bo_alloc(bufmgr, name, size, alignment); } -drm_intel_bo * -drm_intel_bo_alloc_for_render(drm_intel_bufmgr *bufmgr, const char *name, - unsigned long size, unsigned int alignment) +drm_intel_bo *drm_intel_bo_alloc_for_render(drm_intel_bufmgr *bufmgr, + const char *name, + unsigned long size, + unsigned int alignment) { - return bufmgr->bo_alloc_for_render(bufmgr, name, size, alignment); + return bufmgr->bo_alloc_for_render(bufmgr, name, size, alignment); } -void -drm_intel_bo_reference(drm_intel_bo *bo) +void drm_intel_bo_reference(drm_intel_bo *bo) { - bo->bufmgr->bo_reference(bo); + bo->bufmgr->bo_reference(bo); } -void -drm_intel_bo_unreference(drm_intel_bo *bo) +void drm_intel_bo_unreference(drm_intel_bo *bo) { - if (bo == NULL) - return; + if (bo == NULL) + return; - bo->bufmgr->bo_unreference(bo); + bo->bufmgr->bo_unreference(bo); } -int -drm_intel_bo_map(drm_intel_bo *buf, int write_enable) +int drm_intel_bo_map(drm_intel_bo *buf, int write_enable) { - return buf->bufmgr->bo_map(buf, write_enable); + return buf->bufmgr->bo_map(buf, write_enable); } -int -drm_intel_bo_unmap(drm_intel_bo *buf) +int drm_intel_bo_unmap(drm_intel_bo *buf) { - return buf->bufmgr->bo_unmap(buf); + return buf->bufmgr->bo_unmap(buf); } int drm_intel_bo_subdata(drm_intel_bo *bo, unsigned long offset, unsigned long size, const void *data) { - int ret; + int ret; - if (bo->bufmgr->bo_subdata) - return bo->bufmgr->bo_subdata(bo, offset, size, data); - if (size == 0 || data == NULL) - return 0; + if (bo->bufmgr->bo_subdata) + return bo->bufmgr->bo_subdata(bo, offset, size, data); + if (size == 0 || data == NULL) + return 0; - ret = drm_intel_bo_map(bo, 1); - if (ret) - return ret; - memcpy((unsigned char *)bo->virtual + offset, data, size); - drm_intel_bo_unmap(bo); - return 0; + ret = drm_intel_bo_map(bo, 1); + if (ret) + return ret; + memcpy((unsigned char *)bo->virtual + offset, data, size); + drm_intel_bo_unmap(bo); + return 0; } int drm_intel_bo_get_subdata(drm_intel_bo *bo, unsigned long offset, unsigned long size, void *data) { - int ret; - if (bo->bufmgr->bo_subdata) - return bo->bufmgr->bo_get_subdata(bo, offset, size, data); + int ret; + if (bo->bufmgr->bo_subdata) + return bo->bufmgr->bo_get_subdata(bo, offset, size, data); - if (size == 0 || data == NULL) - return 0; + if (size == 0 || data == NULL) + return 0; - ret = drm_intel_bo_map(bo, 0); - if (ret) - return ret; - memcpy(data, (unsigned char *)bo->virtual + offset, size); - drm_intel_bo_unmap(bo); - return 0; + ret = drm_intel_bo_map(bo, 0); + if (ret) + return ret; + memcpy(data, (unsigned char *)bo->virtual + offset, size); + drm_intel_bo_unmap(bo); + return 0; } -void -drm_intel_bo_wait_rendering(drm_intel_bo *bo) +void drm_intel_bo_wait_rendering(drm_intel_bo *bo) { - bo->bufmgr->bo_wait_rendering(bo); + bo->bufmgr->bo_wait_rendering(bo); } -void -drm_intel_bufmgr_destroy(drm_intel_bufmgr *bufmgr) +void drm_intel_bufmgr_destroy(drm_intel_bufmgr *bufmgr) { - bufmgr->destroy(bufmgr); + bufmgr->destroy(bufmgr); } int drm_intel_bo_exec(drm_intel_bo *bo, int used, - drm_clip_rect_t *cliprects, int num_cliprects, - int DR4) + drm_clip_rect_t * cliprects, int num_cliprects, int DR4) { - return bo->bufmgr->bo_exec(bo, used, cliprects, num_cliprects, DR4); + return bo->bufmgr->bo_exec(bo, used, cliprects, num_cliprects, DR4); } -void -drm_intel_bufmgr_set_debug(drm_intel_bufmgr *bufmgr, int enable_debug) +void drm_intel_bufmgr_set_debug(drm_intel_bufmgr *bufmgr, int enable_debug) { - bufmgr->debug = enable_debug; + bufmgr->debug = enable_debug; } -int -drm_intel_bufmgr_check_aperture_space(drm_intel_bo **bo_array, int count) +int drm_intel_bufmgr_check_aperture_space(drm_intel_bo ** bo_array, int count) { return bo_array[0]->bufmgr->check_aperture_space(bo_array, count); } -int -drm_intel_bo_flink(drm_intel_bo *bo, uint32_t *name) +int drm_intel_bo_flink(drm_intel_bo *bo, uint32_t * name) { - if (bo->bufmgr->bo_flink) - return bo->bufmgr->bo_flink(bo, name); + if (bo->bufmgr->bo_flink) + return bo->bufmgr->bo_flink(bo, name); - return -ENODEV; + return -ENODEV; } int @@ -174,43 +164,41 @@ drm_intel_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset, read_domains, write_domain); } -int -drm_intel_bo_pin(drm_intel_bo *bo, uint32_t alignment) +int drm_intel_bo_pin(drm_intel_bo *bo, uint32_t alignment) { - if (bo->bufmgr->bo_pin) - return bo->bufmgr->bo_pin(bo, alignment); + if (bo->bufmgr->bo_pin) + return bo->bufmgr->bo_pin(bo, alignment); - return -ENODEV; + return -ENODEV; } -int -drm_intel_bo_unpin(drm_intel_bo *bo) +int drm_intel_bo_unpin(drm_intel_bo *bo) { - if (bo->bufmgr->bo_unpin) - return bo->bufmgr->bo_unpin(bo); + if (bo->bufmgr->bo_unpin) + return bo->bufmgr->bo_unpin(bo); - return -ENODEV; + return -ENODEV; } -int drm_intel_bo_set_tiling(drm_intel_bo *bo, uint32_t *tiling_mode, +int drm_intel_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode, uint32_t stride) { - if (bo->bufmgr->bo_set_tiling) - return bo->bufmgr->bo_set_tiling(bo, tiling_mode, stride); + if (bo->bufmgr->bo_set_tiling) + return bo->bufmgr->bo_set_tiling(bo, tiling_mode, stride); - *tiling_mode = I915_TILING_NONE; - return 0; + *tiling_mode = I915_TILING_NONE; + return 0; } -int drm_intel_bo_get_tiling(drm_intel_bo *bo, uint32_t *tiling_mode, - uint32_t *swizzle_mode) +int drm_intel_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode, + uint32_t * swizzle_mode) { - if (bo->bufmgr->bo_get_tiling) - return bo->bufmgr->bo_get_tiling(bo, tiling_mode, swizzle_mode); + if (bo->bufmgr->bo_get_tiling) + return bo->bufmgr->bo_get_tiling(bo, tiling_mode, swizzle_mode); - *tiling_mode = I915_TILING_NONE; - *swizzle_mode = I915_BIT_6_SWIZZLE_NONE; - return 0; + *tiling_mode = I915_TILING_NONE; + *swizzle_mode = I915_BIT_6_SWIZZLE_NONE; + return 0; } int drm_intel_bo_disable_reuse(drm_intel_bo *bo) @@ -227,17 +215,14 @@ int drm_intel_bo_busy(drm_intel_bo *bo) return 0; } -int -drm_intel_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo) +int drm_intel_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo) { return bo->bufmgr->bo_references(bo, target_bo); } -int -drm_intel_get_pipe_from_crtc_id (drm_intel_bufmgr *bufmgr, int crtc_id) +int drm_intel_get_pipe_from_crtc_id(drm_intel_bufmgr *bufmgr, int crtc_id) { if (bufmgr->get_pipe_from_crtc_id) return bufmgr->get_pipe_from_crtc_id(bufmgr, crtc_id); return -1; } - diff --git a/libdrm/intel/intel_bufmgr.h b/libdrm/intel/intel_bufmgr.h index cb7196c..9f07a94 100644 --- a/libdrm/intel/intel_bufmgr.h +++ b/libdrm/intel/intel_bufmgr.h @@ -40,37 +40,40 @@ typedef struct _drm_intel_bufmgr drm_intel_bufmgr; typedef struct _drm_intel_bo drm_intel_bo; struct _drm_intel_bo { - /** - * Size in bytes of the buffer object. - * - * The size may be larger than the size originally requested for the - * allocation, such as being aligned to page size. - */ - unsigned long size; - /** - * Alignment requirement for object - * - * Used for GTT mapping & pinning the object. - */ - unsigned long align; - - /** - * Card virtual address (offset from the beginning of the aperture) for the - * object. Only valid while validated. - */ - unsigned long offset; - /** - * Virtual address for accessing the buffer data. Only valid while mapped. - */ - void *virtual; - - /** Buffer manager context associated with this buffer object */ - drm_intel_bufmgr *bufmgr; - - /** - * MM-specific handle for accessing object - */ - int handle; + /** + * Size in bytes of the buffer object. + * + * The size may be larger than the size originally requested for the + * allocation, such as being aligned to page size. + */ + unsigned long size; + + /** + * Alignment requirement for object + * + * Used for GTT mapping & pinning the object. + */ + unsigned long align; + + /** + * Card virtual address (offset from the beginning of the aperture) + * for the object. Only valid while validated. + */ + unsigned long offset; + + /** + * Virtual address for accessing the buffer data. Only valid while + * mapped. + */ + void *virtual; + + /** Buffer manager context associated with this buffer object */ + drm_intel_bufmgr *bufmgr; + + /** + * MM-specific handle for accessing object + */ + int handle; }; drm_intel_bo *drm_intel_bo_alloc(drm_intel_bufmgr *bufmgr, const char *name, @@ -85,28 +88,27 @@ int drm_intel_bo_map(drm_intel_bo *bo, int write_enable); int drm_intel_bo_unmap(drm_intel_bo *bo); int drm_intel_bo_subdata(drm_intel_bo *bo, unsigned long offset, - unsigned long size, const void *data); + unsigned long size, const void *data); int drm_intel_bo_get_subdata(drm_intel_bo *bo, unsigned long offset, - unsigned long size, void *data); + unsigned long size, void *data); void drm_intel_bo_wait_rendering(drm_intel_bo *bo); void drm_intel_bufmgr_set_debug(drm_intel_bufmgr *bufmgr, int enable_debug); void drm_intel_bufmgr_destroy(drm_intel_bufmgr *bufmgr); int drm_intel_bo_exec(drm_intel_bo *bo, int used, - drm_clip_rect_t *cliprects, int num_cliprects, - int DR4); -int drm_intel_bufmgr_check_aperture_space(drm_intel_bo **bo_array, int count); + drm_clip_rect_t * cliprects, int num_cliprects, int DR4); +int drm_intel_bufmgr_check_aperture_space(drm_intel_bo ** bo_array, int count); int drm_intel_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset, drm_intel_bo *target_bo, uint32_t target_offset, uint32_t read_domains, uint32_t write_domain); int drm_intel_bo_pin(drm_intel_bo *bo, uint32_t alignment); int drm_intel_bo_unpin(drm_intel_bo *bo); -int drm_intel_bo_set_tiling(drm_intel_bo *bo, uint32_t *tiling_mode, +int drm_intel_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode, uint32_t stride); -int drm_intel_bo_get_tiling(drm_intel_bo *bo, uint32_t *tiling_mode, - uint32_t *swizzle_mode); -int drm_intel_bo_flink(drm_intel_bo *bo, uint32_t *name); +int drm_intel_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode, + uint32_t * swizzle_mode); +int drm_intel_bo_flink(drm_intel_bo *bo, uint32_t * name); int drm_intel_bo_busy(drm_intel_bo *bo); int drm_intel_bo_disable_reuse(drm_intel_bo *bo); @@ -129,26 +131,29 @@ drm_intel_bufmgr *drm_intel_bufmgr_fake_init(int fd, unsigned long low_offset, void *low_virtual, unsigned long size, - volatile unsigned int *last_dispatch); + volatile unsigned int + *last_dispatch); void drm_intel_bufmgr_fake_set_last_dispatch(drm_intel_bufmgr *bufmgr, - volatile unsigned int *last_dispatch); + volatile unsigned int + *last_dispatch); void drm_intel_bufmgr_fake_set_exec_callback(drm_intel_bufmgr *bufmgr, - int (*exec)(drm_intel_bo *bo, - unsigned int used, - void *priv), + int (*exec) (drm_intel_bo *bo, + unsigned int used, + void *priv), void *priv); void drm_intel_bufmgr_fake_set_fence_callback(drm_intel_bufmgr *bufmgr, - unsigned int (*emit)(void *priv), - void (*wait)(unsigned int fence, - void *priv), + unsigned int (*emit) (void *priv), + void (*wait) (unsigned int fence, + void *priv), void *priv); drm_intel_bo *drm_intel_bo_fake_alloc_static(drm_intel_bufmgr *bufmgr, const char *name, - unsigned long offset, unsigned long size, - void *virtual); + unsigned long offset, + unsigned long size, void *virtual); void drm_intel_bo_fake_disable_backing_store(drm_intel_bo *bo, - void (*invalidate_cb)(drm_intel_bo *bo, - void *ptr), + void (*invalidate_cb) (drm_intel_bo + * bo, + void *ptr), void *ptr); void drm_intel_bufmgr_fake_contended_lock_take(drm_intel_bufmgr *bufmgr); @@ -174,8 +179,8 @@ void drm_intel_bufmgr_fake_evict_all(drm_intel_bufmgr *bufmgr); #define dri_bo_emit_reloc(reloc_bo, read, write, target_offset, \ reloc_offset, target_bo) \ drm_intel_bo_emit_reloc(reloc_bo, reloc_offset, \ - target_bo, target_offset, \ - read, write); + target_bo, target_offset, \ + read, write); #define dri_bo_pin drm_intel_bo_pin #define dri_bo_unpin drm_intel_bo_unpin #define dri_bo_get_tiling drm_intel_bo_get_tiling @@ -196,4 +201,3 @@ void drm_intel_bufmgr_fake_evict_all(drm_intel_bufmgr *bufmgr); /** @{ */ #endif /* INTEL_BUFMGR_H */ - diff --git a/libdrm/intel/intel_bufmgr_fake.c b/libdrm/intel/intel_bufmgr_fake.c index 969c03d..f325482 100644 --- a/libdrm/intel/intel_bufmgr_fake.c +++ b/libdrm/intel/intel_bufmgr_fake.c @@ -54,8 +54,8 @@ #define ALIGN(value, alignment) ((value + alignment - 1) & ~(alignment - 1)) #define DBG(...) do { \ - if (bufmgr_fake->bufmgr.debug) \ - drmMsg(__VA_ARGS__); \ + if (bufmgr_fake->bufmgr.debug) \ + drmMsg(__VA_ARGS__); \ } while (0) /* Internal flags: @@ -72,150 +72,157 @@ */ #define MAX_RELOCS 4096 -struct fake_buffer_reloc -{ - /** Buffer object that the relocation points at. */ - drm_intel_bo *target_buf; - /** Offset of the relocation entry within reloc_buf. */ - uint32_t offset; - /** Cached value of the offset when we last performed this relocation. */ - uint32_t last_target_offset; - /** Value added to target_buf's offset to get the relocation entry. */ - uint32_t delta; - /** Cache domains the target buffer is read into. */ - uint32_t read_domains; - /** Cache domain the target buffer will have dirty cachelines in. */ - uint32_t write_domain; +struct fake_buffer_reloc { + /** Buffer object that the relocation points at. */ + drm_intel_bo *target_buf; + /** Offset of the relocation entry within reloc_buf. */ + uint32_t offset; + /** + * Cached value of the offset when we last performed this relocation. + */ + uint32_t last_target_offset; + /** Value added to target_buf's offset to get the relocation entry. */ + uint32_t delta; + /** Cache domains the target buffer is read into. */ + uint32_t read_domains; + /** Cache domain the target buffer will have dirty cachelines in. */ + uint32_t write_domain; }; struct block { - struct block *next, *prev; - struct mem_block *mem; /* BM_MEM_AGP */ - - /** - * Marks that the block is currently in the aperture and has yet to be - * fenced. - */ - unsigned on_hardware:1; - /** - * Marks that the block is currently fenced (being used by rendering) and - * can't be freed until @fence is passed. - */ - unsigned fenced:1; - - /** Fence cookie for the block. */ - unsigned fence; /* Split to read_fence, write_fence */ - - drm_intel_bo *bo; - void *virtual; + struct block *next, *prev; + struct mem_block *mem; /* BM_MEM_AGP */ + + /** + * Marks that the block is currently in the aperture and has yet to be + * fenced. + */ + unsigned on_hardware:1; + /** + * Marks that the block is currently fenced (being used by rendering) + * and can't be freed until @fence is passed. + */ + unsigned fenced:1; + + /** Fence cookie for the block. */ + unsigned fence; /* Split to read_fence, write_fence */ + + drm_intel_bo *bo; + void *virtual; }; typedef struct _bufmgr_fake { - drm_intel_bufmgr bufmgr; - - pthread_mutex_t lock; - - unsigned long low_offset; - unsigned long size; - void *virtual; - - struct mem_block *heap; - - unsigned buf_nr; /* for generating ids */ - -- To UNSUBSCRIBE, email to [email protected] with a subject of "unsubscribe". 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