> -----Original Message-----
> From: Power, Ciara <[email protected]>
> Sent: Tuesday, March 5, 2024 5:26 PM
> To: [email protected]
> Cc: [email protected]; Power, Ciara <[email protected]>; Nayak,
> Nishikanta <[email protected]>; Ji, Kai <[email protected]>
> Subject: [PATCH] common/qat: fix undefined macro
>
> When using RTE_ENABLE_ASSERT and debug mode, an undefined macro
> error appeared for ICP_QAT_FW_SYM_COMM_ADDR_SGL.
> This was not being defined, but is now added to the header file.
>
> Bugzilla ID: 1395
> Fixes: e9271821e489 ("common/qat: support GEN LCE device")
>
> Signed-off-by: Ciara Power <[email protected]>
>
> ---
> Cc: [email protected]
> ---
> drivers/common/qat/qat_adf/icp_qat_fw_la.h | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/common/qat/qat_adf/icp_qat_fw_la.h
> b/drivers/common/qat/qat_adf/icp_qat_fw_la.h
> index 67fc25c919..fe32b66c50 100644
> --- a/drivers/common/qat/qat_adf/icp_qat_fw_la.h
> +++ b/drivers/common/qat/qat_adf/icp_qat_fw_la.h
> @@ -111,6 +111,7 @@ struct icp_qat_fw_la_bulk_req { #define
> ICP_QAT_FW_SYM_IV_IN_DESC_VALID 1 #define
> ICP_QAT_FW_SYM_DIRECTION_BITPOS 15 #define
> ICP_QAT_FW_SYM_DIRECTION_MASK 0x1
> +#define ICP_QAT_FW_SYM_COMM_ADDR_SGL 1
>
> /* In GEN_LCE AEAD AES GCM Algorithm has ID 0 */ #define
> QAT_LA_CRYPTO_AEAD_AES_GCM_GEN_LCE 0
> --
> 2.25.1
Acked-by: Nishikant Nayak <[email protected]>
