On Wed, 10 Sep 2025 14:57:20 -0400 Ed Czeck <[email protected]> wrote:
> use 4-K page aligned buffers to reduce PCIe requests > reduce message spew > attempt to allocate smaller chunks of buffers during starvation > > Signed-off-by: Ed Czeck <[email protected]> > --- > v2: > - reduced message to single line. > - Added comments on buffer alignment. PCIe devices deal with page > size of 4096 bytes. By aligning this buffer to a 4K boundary, we > will reduce the number of PCIe read requests. It would be clearer if there was a #define for the magic 4096 size. Is the IOMMU page size? The PCI devices themselves don't usually have page visibility. Alignment in this case is really a workaround for "don't cross the boundary". It looks like the rte_malloc library doesn't have better way to express that.
