The branch stable/13 has been updated by np: URL: https://cgit.FreeBSD.org/src/commit/?id=d8034cee46f3d547ad3fcd1e93024d27479b6e38
commit d8034cee46f3d547ad3fcd1e93024d27479b6e38 Author: Navdeep Parhar <[email protected]> AuthorDate: 2021-09-07 20:39:44 +0000 Commit: Navdeep Parhar <[email protected]> CommitDate: 2021-10-20 17:48:22 +0000 cxgbe(4): Display HMA information in meminfo. This should have been added with initial T6 support many years ago. Sponsored by: Chelsio Communications (cherry picked from commit 83a611e09238ead5a765c0ea2c02699fe8175756) --- sys/dev/cxgbe/common/common.h | 2 +- sys/dev/cxgbe/t4_main.c | 18 +++++++++++++----- 2 files changed, 14 insertions(+), 6 deletions(-) diff --git a/sys/dev/cxgbe/common/common.h b/sys/dev/cxgbe/common/common.h index c132cb779204..07d8ab2b40f0 100644 --- a/sys/dev/cxgbe/common/common.h +++ b/sys/dev/cxgbe/common/common.h @@ -49,7 +49,7 @@ enum { T5_REGMAP_SIZE = (332 * 1024), }; -enum { MEM_EDC0, MEM_EDC1, MEM_MC, MEM_MC0 = MEM_MC, MEM_MC1 }; +enum { MEM_EDC0, MEM_EDC1, MEM_MC, MEM_MC0 = MEM_MC, MEM_MC1, MEM_HMA }; enum dev_master { MASTER_CANT, MASTER_MAY, MASTER_MUST }; diff --git a/sys/dev/cxgbe/t4_main.c b/sys/dev/cxgbe/t4_main.c index 2fa54909aa5a..853bc2b5d58a 100644 --- a/sys/dev/cxgbe/t4_main.c +++ b/sys/dev/cxgbe/t4_main.c @@ -9591,7 +9591,9 @@ sysctl_meminfo(SYSCTL_HANDLER_ARGS) struct sbuf *sb; int rc, i, n; uint32_t lo, hi, used, alloc; - static const char *memory[] = {"EDC0:", "EDC1:", "MC:", "MC0:", "MC1:"}; + static const char *memory[] = { + "EDC0:", "EDC1:", "MC:", "MC0:", "MC1:", "HMA:" + }; static const char *region[] = { "DBQ contexts:", "IMSG contexts:", "FLM cache:", "TCBs:", "Pstructs:", "Timers:", "Rx FL:", "Tx FL:", "Pstruct FL:", @@ -9644,19 +9646,25 @@ sysctl_meminfo(SYSCTL_HANDLER_ARGS) if (lo & F_EXT_MEM_ENABLE) { hi = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR); avail[i].base = G_EXT_MEM_BASE(hi) << 20; - avail[i].limit = avail[i].base + - (G_EXT_MEM_SIZE(hi) << 20); + avail[i].limit = avail[i].base + (G_EXT_MEM_SIZE(hi) << 20); avail[i].idx = is_t5(sc) ? 3 : 2; /* Call it MC0 for T5 */ i++; } if (is_t5(sc) && lo & F_EXT_MEM1_ENABLE) { hi = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR); avail[i].base = G_EXT_MEM1_BASE(hi) << 20; - avail[i].limit = avail[i].base + - (G_EXT_MEM1_SIZE(hi) << 20); + avail[i].limit = avail[i].base + (G_EXT_MEM1_SIZE(hi) << 20); avail[i].idx = 4; i++; } + if (is_t6(sc) && lo & F_HMA_MUX) { + hi = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR); + avail[i].base = G_EXT_MEM1_BASE(hi) << 20; + avail[i].limit = avail[i].base + (G_EXT_MEM1_SIZE(hi) << 20); + avail[i].idx = 5; + i++; + } + MPASS(i <= nitems(avail)); if (!i) /* no memory available */ goto done; qsort(avail, i, sizeof(struct mem_desc), mem_desc_cmp);
