The branch main has been updated by adrian: URL: https://cgit.FreeBSD.org/src/commit/?id=777963afb5a0dba75cdd7117d3070d9486b2ee96
commit 777963afb5a0dba75cdd7117d3070d9486b2ee96 Author: Adrian Chadd <[email protected]> AuthorDate: 2021-12-28 02:25:32 +0000 Commit: Adrian Chadd <[email protected]> CommitDate: 2021-12-28 02:25:32 +0000 qcom_dwc3: add initial Qualcomm SoC DWC3 controller glue This adds some very simple DWC3 glue for the IPQ4018/IPQ4019. Other chipsets introduce reset line iteration, some further clock line iteration and some customisations; I'll look at adding those later. This is enough to finally bring up USB 3.0 on my IPQ4018 ASUS RT-58U router. --- sys/arm/conf/std.qca | 7 ++ sys/arm/qualcomm/std.ipq4018 | 2 + sys/dev/qcom_dwc3/qcom_dwc3.c | 180 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 189 insertions(+) diff --git a/sys/arm/conf/std.qca b/sys/arm/conf/std.qca index c835b3c94616..5cc6ac8ff9aa 100644 --- a/sys/arm/conf/std.qca +++ b/sys/arm/conf/std.qca @@ -65,3 +65,10 @@ options ARM_FORCE_DBG_MONITOR_DISABLE # USB PHY support device qcom_ipq4018_hs_usbphy device qcom_ipq4018_ss_usbphy + +# USB support +device usb +device xhci +device dwc3 +device qcom_dwc3 +options USB_HOST_ALIGN=64 diff --git a/sys/arm/qualcomm/std.ipq4018 b/sys/arm/qualcomm/std.ipq4018 index ed771179b3a0..d567b041078c 100644 --- a/sys/arm/qualcomm/std.ipq4018 +++ b/sys/arm/qualcomm/std.ipq4018 @@ -6,6 +6,8 @@ arm/qualcomm/qcom_cpu_kpssv2.c optional smp arm/qualcomm/ipq4018_usb_hs_phy.c optional qcom_ipq4018_hs_usbphy arm/qualcomm/ipq4018_usb_ss_phy.c optional qcom_ipq4018_ss_usbphy +dev/qcom_dwc3/qcom_dwc3.c optional qcom_dwc3 + dev/qcom_rnd/qcom_rnd.c optional qcom_rnd dev/qcom_qup/qcom_spi.c optional qcom_qup_spi diff --git a/sys/dev/qcom_dwc3/qcom_dwc3.c b/sys/dev/qcom_dwc3/qcom_dwc3.c new file mode 100644 index 000000000000..b027bc609453 --- /dev/null +++ b/sys/dev/qcom_dwc3/qcom_dwc3.c @@ -0,0 +1,180 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause-FreeBSD + * + * Copyright (c) 2021 Adrian Chadd <[email protected]> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +/* + * Qualcomm DWC3 glue + */ + +#include <sys/cdefs.h> +__FBSDID("$FreeBSD$"); + +#include <sys/param.h> +#include <sys/systm.h> +#include <sys/bus.h> +#include <sys/rman.h> +#include <sys/kernel.h> +#include <sys/module.h> +#include <sys/gpio.h> +#include <machine/bus.h> + +#include <dev/fdt/simplebus.h> + +#include <dev/fdt/fdt_common.h> +#include <dev/ofw/ofw_bus.h> +#include <dev/ofw/ofw_bus_subr.h> +#include <dev/ofw/ofw_subr.h> + +#include <dev/extres/clk/clk.h> +#include <dev/extres/hwreset/hwreset.h> +#include <dev/extres/phy/phy_usb.h> +#include <dev/extres/syscon/syscon.h> + +static struct ofw_compat_data compat_data[] = { + { "qcom,dwc3", 1}, + { NULL, 0 } +}; + +struct qcom_dwc3_softc { + struct simplebus_softc sc; + device_t dev; + clk_t clk_master; + clk_t clk_sleep; + clk_t clk_mock_utmi; + int type; +}; + +static int +qcom_dwc3_probe(device_t dev) +{ + phandle_t node; + + if (!ofw_bus_status_okay(dev)) + return (ENXIO); + + if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) + return (ENXIO); + + /* Binding says that we need a child node for the actual dwc3 controller */ + node = ofw_bus_get_node(dev); + if (OF_child(node) <= 0) + return (ENXIO); + + device_set_desc(dev, "Qualcomm DWC3"); + return (BUS_PROBE_DEFAULT); +} + +static int +qcom_dwc3_attach(device_t dev) +{ + struct qcom_dwc3_softc *sc; + device_t cdev; + phandle_t node, child; + int err; + + sc = device_get_softc(dev); + sc->dev = dev; + node = ofw_bus_get_node(dev); + sc->type = ofw_bus_search_compatible(dev, compat_data)->ocd_data; + + /* Mandatory clocks */ + if (clk_get_by_ofw_name(dev, 0, "master", &sc->clk_master) != 0) { + device_printf(dev, "Cannot get master clock\n"); + return (ENXIO); + } + + if (clk_get_by_ofw_name(dev, 0, "sleep", &sc->clk_sleep) != 0) { + device_printf(dev, "Cannot get sleep clock\n"); + return (ENXIO); + } + + if (clk_get_by_ofw_name(dev, 0, "mock_utmi", &sc->clk_mock_utmi) != 0) { + device_printf(dev, "Cannot get mock_utmi clock\n"); + return (ENXIO); + } + + /* + * TODO: when we support optional reset blocks, take things + * out of reset (well, put them into reset, then take out of reset.) + */ + + /* + * Now, iterate over the clocks and enable them. + */ + err = clk_enable(sc->clk_master); + if (err != 0) { + device_printf(dev, "Could not enable clock %s\n", + clk_get_name(sc->clk_master)); + return (ENXIO); + } + err = clk_enable(sc->clk_sleep); + if (err != 0) { + device_printf(dev, "Could not enable clock %s\n", + clk_get_name(sc->clk_sleep)); + return (ENXIO); + } + err = clk_enable(sc->clk_mock_utmi); + if (err != 0) { + device_printf(dev, "Could not enable clock %s\n", + clk_get_name(sc->clk_mock_utmi)); + return (ENXIO); + } + + /* + * Rest is glue code. + */ + + simplebus_init(dev, node); + if (simplebus_fill_ranges(node, &sc->sc) < 0) { + device_printf(dev, "could not get ranges\n"); + return (ENXIO); + } + + for (child = OF_child(node); child > 0; child = OF_peer(child)) { + cdev = simplebus_add_device(dev, child, 0, NULL, -1, NULL); + if (cdev != NULL) + device_probe_and_attach(cdev); + } + + return (bus_generic_attach(dev)); +} + +static device_method_t qcom_dwc3_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, qcom_dwc3_probe), + DEVMETHOD(device_attach, qcom_dwc3_attach), + /* XXX TODO suspend */ + /* XXX TODO resume */ + + DEVMETHOD_END +}; + +static devclass_t qcom_dwc3_devclass; + +DEFINE_CLASS_1(qcom_dwc3, qcom_dwc3_driver, qcom_dwc3_methods, + sizeof(struct qcom_dwc3_softc), simplebus_driver); +DRIVER_MODULE(qcom_dwc3, simplebus, qcom_dwc3_driver, qcom_dwc3_devclass, + 0, 0);
