The branch stable/13 has been updated by manu: URL: https://cgit.FreeBSD.org/src/commit/?id=a412da4f9e7e48067ab1cdc5986bf13497129085
commit a412da4f9e7e48067ab1cdc5986bf13497129085 Author: Søren Schmidt <[email protected]> AuthorDate: 2022-08-16 12:24:44 +0000 Commit: Emmanuel Vadot <[email protected]> CommitDate: 2023-02-02 11:17:19 +0000 Add support for RockChip RK356X to DWC3 driver. For RK356x platform, we can set bit 26 of DWC3_GUCTL1 register for usb 2.0 device. Reviewed by: manu Differential Revision: https://reviews.freebsd.org/D36211 (cherry picked from commit 1331c0f44b6a3b6dec1fbd638103fa15bffac5d8) --- sys/arm64/rockchip/rk_dwc3.c | 6 +----- sys/dev/usb/controller/dwc3.c | 9 ++++++++- sys/dev/usb/controller/dwc3.h | 1 + 3 files changed, 10 insertions(+), 6 deletions(-) diff --git a/sys/arm64/rockchip/rk_dwc3.c b/sys/arm64/rockchip/rk_dwc3.c index d63ba67907f8..72292e9f8902 100644 --- a/sys/arm64/rockchip/rk_dwc3.c +++ b/sys/arm64/rockchip/rk_dwc3.c @@ -141,11 +141,7 @@ rk_dwc3_attach(device_t dev) clk_get_name(sc->clk_bus)); return (ENXIO); } - if (sc->type == RK3399) { - if (clk_get_by_ofw_name(dev, 0, "grf_clk", &sc->clk_grf) != 0) { - device_printf(dev, "Cannot get grf_clk clock\n"); - return (ENXIO); - } + if (clk_get_by_ofw_name(dev, 0, "grf_clk", &sc->clk_grf) == 0) { err = clk_enable(sc->clk_grf); if (err != 0) { device_printf(dev, "Could not enable clock %s\n", diff --git a/sys/dev/usb/controller/dwc3.c b/sys/dev/usb/controller/dwc3.c index 19237ef4c11d..2e8f868bc47b 100644 --- a/sys/dev/usb/controller/dwc3.c +++ b/sys/dev/usb/controller/dwc3.c @@ -366,6 +366,7 @@ snps_dwc3_common_attach(device_t dev, bool is_fdt) #ifdef FDT phandle_t node; phy_t usb2_phy, usb3_phy; + uint32_t reg; #endif int error, rid; @@ -403,7 +404,13 @@ snps_dwc3_common_attach(device_t dev, bool is_fdt) error = phy_get_by_ofw_name(dev, node, "usb3-phy", &usb3_phy); if (error == 0 && usb3_phy != NULL) phy_enable(usb3_phy); - + else { + reg = DWC3_READ(sc, DWC3_GUCTL1); + if (bootverbose) + device_printf(dev, "Forcing USB2 clock only\n"); + reg |= DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK; + DWC3_WRITE(sc, DWC3_GUCTL1, reg); + } snps_dwc3_configure_phy(sc, node); skip_phys: #endif diff --git a/sys/dev/usb/controller/dwc3.h b/sys/dev/usb/controller/dwc3.h index 83951d327c8c..21a87a1917ee 100644 --- a/sys/dev/usb/controller/dwc3.h +++ b/sys/dev/usb/controller/dwc3.h @@ -49,6 +49,7 @@ #define DWC3_GUCTL1 0xc11c #define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS (1 << 28) +#define DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK (1 << 26) #define DWC3_GSNPSID 0xc120 #define DWC3_GGPIO 0xc124
