The branch main has been updated by kib: URL: https://cgit.FreeBSD.org/src/commit/?id=fc8da73b93be3f5cc50f7607dbcfc1edb911de65
commit fc8da73b93be3f5cc50f7607dbcfc1edb911de65 Author: Konstantin Belousov <[email protected]> AuthorDate: 2024-06-09 14:08:28 +0000 Commit: Konstantin Belousov <[email protected]> CommitDate: 2024-09-04 21:50:18 +0000 x86 iommu x86_unit_common: expand hw completion write-out area to 8 bytes in preparation to share it with AMD IOMMU. AMD writes out 8 bytes. We use 32-bit completion sequence numbers, and CPUs are little-endian. So the expansion is acceptable on Intel. Sponsored by: Advanced Micro Devices (AMD) Sponsored by: The FreeBSD Foundation MFC after: 1 week --- sys/x86/iommu/intel_drv.c | 4 ++-- sys/x86/iommu/x86_iommu.h | 10 ++++++++-- 2 files changed, 10 insertions(+), 4 deletions(-) diff --git a/sys/x86/iommu/intel_drv.c b/sys/x86/iommu/intel_drv.c index 9fa1b3f98dc6..66d99748888f 100644 --- a/sys/x86/iommu/intel_drv.c +++ b/sys/x86/iommu/intel_drv.c @@ -1302,7 +1302,7 @@ dmar_print_one(int idx, bool show_domains, bool show_mappings) db_printf("qi is enabled: queue @0x%jx (IQA 0x%jx) " "size 0x%jx\n" " head 0x%x tail 0x%x avail 0x%x status 0x%x ctrl 0x%x\n" - " hw compl 0x%x@%p/phys@%jx next seq 0x%x gen 0x%x\n", + " hw compl 0x%jx@%p/phys@%jx next seq 0x%x gen 0x%x\n", (uintmax_t)unit->x86c.inv_queue, (uintmax_t)dmar_read8(unit, DMAR_IQA_REG), (uintmax_t)unit->x86c.inv_queue_size, @@ -1311,7 +1311,7 @@ dmar_print_one(int idx, bool show_domains, bool show_mappings) unit->x86c.inv_queue_avail, dmar_read4(unit, DMAR_ICS_REG), dmar_read4(unit, DMAR_IECTL_REG), - unit->x86c.inv_waitd_seq_hw, + (uintmax_t)unit->x86c.inv_waitd_seq_hw, &unit->x86c.inv_waitd_seq_hw, (uintmax_t)unit->x86c.inv_waitd_seq_hw_phys, unit->x86c.inv_waitd_seq, diff --git a/sys/x86/iommu/x86_iommu.h b/sys/x86/iommu/x86_iommu.h index eb1bbafbeb77..966a13c19b6e 100644 --- a/sys/x86/iommu/x86_iommu.h +++ b/sys/x86/iommu/x86_iommu.h @@ -101,8 +101,14 @@ struct x86_unit_common { vm_size_t inv_queue_size; uint32_t inv_queue_avail; uint32_t inv_queue_tail; - volatile uint32_t inv_waitd_seq_hw; /* hw writes there on wait - descr completion */ + + /* + * Hw writes there on completion of wait descriptor + * processing. Intel writes 4 bytes, while AMD does the + * 8-bytes write. Due to little-endian, and use of 4-byte + * sequence numbers, the difference does not matter for us. + */ + volatile uint64_t inv_waitd_seq_hw; uint64_t inv_waitd_seq_hw_phys; uint32_t inv_waitd_seq; /* next sequence number to use for wait descr */
