The branch main has been updated by andrew:
URL:
https://cgit.FreeBSD.org/src/commit/?id=18db17f5ec86f6473f40eb496739773f4c053ab2
commit 18db17f5ec86f6473f40eb496739773f4c053ab2
Author: Andrew Turner <and...@freebsd.org>
AuthorDate: 2025-05-27 19:55:15 +0000
Commit: Andrew Turner <and...@freebsd.org>
CommitDate: 2025-05-27 19:55:15 +0000
arm64: Make all the PMCR_EL0 fields 64-bit
The register is 64-bit so make sure the fields are too.
Sponsored by: Arm Ltd
Differential Revision: https://reviews.freebsd.org/D50429
---
sys/arm64/include/armreg.h | 20 ++++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/sys/arm64/include/armreg.h b/sys/arm64/include/armreg.h
index df6f7bb7f47b..1571fe273e16 100644
--- a/sys/arm64/include/armreg.h
+++ b/sys/arm64/include/armreg.h
@@ -2370,17 +2370,17 @@
#define PMCR_EL0_CRn 9
#define PMCR_EL0_CRm 12
#define PMCR_EL0_op2 0
-#define PMCR_E (1 << 0) /* Enable all counters
*/
-#define PMCR_P (1 << 1) /* Reset all counters
*/
-#define PMCR_C (1 << 2) /* Clock counter reset
*/
-#define PMCR_D (1 << 3) /* CNTR counts every
64 clk cycles */
-#define PMCR_X (1 << 4) /* Export to ext.
monitoring (ETM) */
-#define PMCR_DP (1 << 5) /* Disable CCNT if
non-invasive debug*/
-#define PMCR_LC (1 << 6) /* Long cycle count
enable */
+#define PMCR_E (1ul << 0) /* Enable all
counters */
+#define PMCR_P (1ul << 1) /* Reset all
counters */
+#define PMCR_C (1ul << 2) /* Clock counter
reset */
+#define PMCR_D (1ul << 3) /* CNTR counts every
64 clk cycles */
+#define PMCR_X (1ul << 4) /* Export to ext.
monitoring (ETM) */
+#define PMCR_DP (1ul << 5) /* Disable CCNT if
non-invasive debug*/
+#define PMCR_LC (1ul << 6) /* Long cycle count
enable */
#define PMCR_N_SHIFT 11 /* Number of counters
implemented */
-#define PMCR_N_MASK (0x1f << PMCR_N_SHIFT)
+#define PMCR_N_MASK (0x1ful << PMCR_N_SHIFT)
#define PMCR_IDCODE_SHIFT 16 /* Identification code
*/
-#define PMCR_IDCODE_MASK (0xff << PMCR_IDCODE_SHIFT)
+#define PMCR_IDCODE_MASK (0xfful << PMCR_IDCODE_SHIFT)
#define PMCR_IDCODE_CORTEX_A57 0x01
#define PMCR_IDCODE_CORTEX_A72 0x02
#define PMCR_IDCODE_CORTEX_A53 0x03
@@ -2393,7 +2393,7 @@
#define PMCR_IDCODE_NEOVERSE_E1 0x46
#define PMCR_IDCODE_CORTEX_A75 0x4a
#define PMCR_IMP_SHIFT 24 /* Implementer code */
-#define PMCR_IMP_MASK (0xff << PMCR_IMP_SHIFT)
+#define PMCR_IMP_MASK (0xfful << PMCR_IMP_SHIFT)
#define PMCR_IMP_ARM 0x41
/* PMEVCNTR<n>_EL0 */
