The branch stable/13 has been updated by kgalazka:
URL:
https://cgit.FreeBSD.org/src/commit/?id=00daa1b56a8b069dbf335d383b29a845bc616bd3
commit 00daa1b56a8b069dbf335d383b29a845bc616bd3
Author: Eric Joyner <e...@freebsd.org>
AuthorDate: 2024-08-29 22:41:20 +0000
Commit: Krzysztof Galazka <kgala...@freebsd.org>
CommitDate: 2025-07-24 14:17:53 +0000
ice: Update to 1.42.1-k
Summary:
- Adds E830 device support
- Adds pre-release E825C support (for the Ethernet device included in
an upcoming Xeon D platform)
- Add sysctl for E810 devices to print out PHY debug statistics (mostly
for FEC debugging)
- Adds per-TX-queue tso counter sysctl to count how many times a TSO offload
was requested for a packet, matching other Intel drivers
- Various bug fixes
Signed-off-by: Eric Joyner <e...@freebsd.org>
Tested by: Jeffrey Pieper <jeffrey.e.pie...@intel.com>
Relnotes: yes
Sponsored by: Intel Corporation
Differential Revisison: https://reviews.freebsd.org/D46949
(cherry picked from commit f2635e844dd138ac9dfba676f27d41750049af26)
---
sys/dev/ice/ice_adminq_cmd.h | 191 ++-
sys/dev/ice/ice_bitops.h | 4 +-
sys/dev/ice/ice_common.c | 967 ++++++++++------
sys/dev/ice/ice_common.h | 189 +--
sys/dev/ice/ice_common_txrx.h | 2 +-
sys/dev/ice/ice_controlq.c | 143 ++-
sys/dev/ice/ice_controlq.h | 24 +-
sys/dev/ice/ice_dcb.c | 90 +-
sys/dev/ice/ice_dcb.h | 42 +-
sys/dev/ice/ice_ddp_common.c | 123 +-
sys/dev/ice/ice_ddp_common.h | 19 +-
sys/dev/ice/ice_devids.h | 38 +-
sys/dev/ice/ice_drv_info.h | 49 +-
sys/dev/ice/ice_features.h | 3 +
sys/dev/ice/ice_flex_pipe.c | 266 ++---
sys/dev/ice/ice_flex_pipe.h | 38 +-
sys/dev/ice/ice_flow.c | 100 +-
sys/dev/ice/ice_flow.h | 14 +-
sys/dev/ice/ice_fw_logging.c | 4 +-
sys/dev/ice/ice_fwlog.c | 39 +-
sys/dev/ice/ice_fwlog.h | 12 +-
sys/dev/ice/ice_hw_autogen.h | 2557 +++++++++++++++++++++++++++++++++++------
sys/dev/ice/ice_iflib.h | 1 -
sys/dev/ice/ice_lan_tx_rx.h | 8 +-
sys/dev/ice/ice_lib.c | 1113 +++++++++++++++---
sys/dev/ice/ice_lib.h | 109 +-
sys/dev/ice/ice_nvm.c | 374 +++---
sys/dev/ice/ice_nvm.h | 56 +-
sys/dev/ice/ice_rdma.c | 2 +-
sys/dev/ice/ice_sbq_cmd.h | 120 ++
sys/dev/ice/ice_sched.c | 487 ++++----
sys/dev/ice/ice_sched.h | 102 +-
sys/dev/ice/ice_strings.c | 4 +-
sys/dev/ice/ice_switch.c | 304 ++---
sys/dev/ice/ice_switch.h | 93 +-
sys/dev/ice/ice_type.h | 36 +-
sys/dev/ice/ice_vlan_mode.c | 22 +-
sys/dev/ice/ice_vlan_mode.h | 2 +-
sys/dev/ice/if_ice_iflib.c | 59 +-
sys/dev/ice/virtchnl.h | 28 +
40 files changed, 5678 insertions(+), 2156 deletions(-)
diff --git a/sys/dev/ice/ice_adminq_cmd.h b/sys/dev/ice/ice_adminq_cmd.h
index 70b56144faf2..6225abc0f38b 100644
--- a/sys/dev/ice/ice_adminq_cmd.h
+++ b/sys/dev/ice/ice_adminq_cmd.h
@@ -187,7 +187,7 @@ struct ice_aqc_list_caps_elem {
#define ICE_AQC_CAPS_ROCEV2_LAG 0x0092
#define ICE_AQC_BIT_ROCEV2_LAG 0x01
#define ICE_AQC_BIT_SRIOV_LAG 0x02
-
+#define ICE_AQC_CAPS_NEXT_CLUSTER_ID 0x0096
u8 major_ver;
u8 minor_ver;
/* Number of resources described by this capability */
@@ -320,7 +320,12 @@ struct ice_aqc_set_port_params {
(0x3F << ICE_AQC_SET_P_PARAMS_LOGI_PORT_ID_S)
#define ICE_AQC_SET_P_PARAMS_IS_LOGI_PORT BIT(14)
#define ICE_AQC_SET_P_PARAMS_SWID_VALID BIT(15)
- u8 reserved[10];
+ u8 lb_mode;
+#define ICE_AQC_SET_P_PARAMS_LOOPBACK_MODE_VALID BIT(2)
+#define ICE_AQC_SET_P_PARAMS_LOOPBACK_MODE_NORMAL 0x00
+#define ICE_AQC_SET_P_PARAMS_LOOPBACK_MODE_NO 0x01
+#define ICE_AQC_SET_P_PARAMS_LOOPBACK_MODE_HIGH 0x02
+ u8 reserved[9];
};
/* These resource type defines are used for all switch resource
@@ -1389,7 +1394,18 @@ struct ice_aqc_get_phy_caps {
#define ICE_PHY_TYPE_HIGH_100G_CAUI2 BIT_ULL(2)
#define ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC BIT_ULL(3)
#define ICE_PHY_TYPE_HIGH_100G_AUI2 BIT_ULL(4)
-#define ICE_PHY_TYPE_HIGH_MAX_INDEX 4
+#define ICE_PHY_TYPE_HIGH_200G_CR4_PAM4 BIT_ULL(5)
+#define ICE_PHY_TYPE_HIGH_200G_SR4 BIT_ULL(6)
+#define ICE_PHY_TYPE_HIGH_200G_FR4 BIT_ULL(7)
+#define ICE_PHY_TYPE_HIGH_200G_LR4 BIT_ULL(8)
+#define ICE_PHY_TYPE_HIGH_200G_DR4 BIT_ULL(9)
+#define ICE_PHY_TYPE_HIGH_200G_KR4_PAM4 BIT_ULL(10)
+#define ICE_PHY_TYPE_HIGH_200G_AUI4_AOC_ACC BIT_ULL(11)
+#define ICE_PHY_TYPE_HIGH_200G_AUI4 BIT_ULL(12)
+#define ICE_PHY_TYPE_HIGH_200G_AUI8_AOC_ACC BIT_ULL(13)
+#define ICE_PHY_TYPE_HIGH_200G_AUI8 BIT_ULL(14)
+#define ICE_PHY_TYPE_HIGH_400GBASE_FR8 BIT_ULL(15)
+#define ICE_PHY_TYPE_HIGH_MAX_INDEX 15
struct ice_aqc_get_phy_caps_data {
__le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */
@@ -1541,11 +1557,14 @@ struct ice_aqc_get_link_status {
enum ice_get_link_status_data_version {
ICE_GET_LINK_STATUS_DATA_V1 = 1,
+ ICE_GET_LINK_STATUS_DATA_V2 = 2,
};
#define ICE_GET_LINK_STATUS_DATALEN_V1 32
+#define ICE_GET_LINK_STATUS_DATALEN_V2 56
/* Get link status response data structure, also used for Link Status Event */
+#pragma pack(1)
struct ice_aqc_get_link_status_data {
u8 topo_media_conflict;
#define ICE_AQ_LINK_TOPO_CONFLICT BIT(0)
@@ -1618,7 +1637,7 @@ struct ice_aqc_get_link_status_data {
#define ICE_AQ_LINK_PWR_QSFP_CLASS_3 2
#define ICE_AQ_LINK_PWR_QSFP_CLASS_4 3
__le16 link_speed;
-#define ICE_AQ_LINK_SPEED_M 0x7FF
+#define ICE_AQ_LINK_SPEED_M 0xFFF
#define ICE_AQ_LINK_SPEED_10MB BIT(0)
#define ICE_AQ_LINK_SPEED_100MB BIT(1)
#define ICE_AQ_LINK_SPEED_1000MB BIT(2)
@@ -1630,12 +1649,37 @@ struct ice_aqc_get_link_status_data {
#define ICE_AQ_LINK_SPEED_40GB BIT(8)
#define ICE_AQ_LINK_SPEED_50GB BIT(9)
#define ICE_AQ_LINK_SPEED_100GB BIT(10)
+#define ICE_AQ_LINK_SPEED_200GB BIT(11)
#define ICE_AQ_LINK_SPEED_UNKNOWN BIT(15)
- __le32 reserved3; /* Aligns next field to 8-byte boundary */
+ __le16 reserved3; /* Aligns next field to 8-byte boundary */
+ u8 ext_fec_status;
+#define ICE_AQ_LINK_RS_272_FEC_EN BIT(0) /* RS 272 FEC enabled */
+ u8 reserved4;
__le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */
__le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */
+ /* Get link status version 2 link partner data */
+ __le64 lp_phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */
+ __le64 lp_phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */
+ u8 lp_fec_adv;
+#define ICE_AQ_LINK_LP_10G_KR_FEC_CAP BIT(0)
+#define ICE_AQ_LINK_LP_25G_KR_FEC_CAP BIT(1)
+#define ICE_AQ_LINK_LP_RS_528_FEC_CAP BIT(2)
+#define ICE_AQ_LINK_LP_50G_KR_272_FEC_CAP BIT(3)
+#define ICE_AQ_LINK_LP_100G_KR_272_FEC_CAP BIT(4)
+#define ICE_AQ_LINK_LP_200G_KR_272_FEC_CAP BIT(5)
+ u8 lp_fec_req;
+#define ICE_AQ_LINK_LP_10G_KR_FEC_REQ BIT(0)
+#define ICE_AQ_LINK_LP_25G_KR_FEC_REQ BIT(1)
+#define ICE_AQ_LINK_LP_RS_528_FEC_REQ BIT(2)
+#define ICE_AQ_LINK_LP_KR_272_FEC_REQ BIT(3)
+ u8 lp_flowcontrol;
+#define ICE_AQ_LINK_LP_PAUSE_ADV BIT(0)
+#define ICE_AQ_LINK_LP_ASM_DIR_ADV BIT(1)
+ u8 reserved[5];
};
+#pragma pack()
+
/* Set event mask command (direct 0x0613) */
struct ice_aqc_set_event_mask {
u8 lport_num;
@@ -1793,14 +1837,46 @@ struct ice_aqc_dnl_call_command {
u8 ctx; /* Used in command, reserved in response */
u8 reserved;
__le16 activity_id;
+#define ICE_AQC_ACT_ID_DNL 0x1129
__le32 reserved1;
__le32 addr_high;
__le32 addr_low;
};
+struct ice_aqc_dnl_equa_param {
+ __le16 data_in;
+#define ICE_AQC_RX_EQU_SHIFT 8
+#define ICE_AQC_RX_EQU_PRE2 (0x10 << ICE_AQC_RX_EQU_SHIFT)
+#define ICE_AQC_RX_EQU_PRE1 (0x11 << ICE_AQC_RX_EQU_SHIFT)
+#define ICE_AQC_RX_EQU_POST1 (0x12 << ICE_AQC_RX_EQU_SHIFT)
+#define ICE_AQC_RX_EQU_BFLF (0x13 << ICE_AQC_RX_EQU_SHIFT)
+#define ICE_AQC_RX_EQU_BFHF (0x14 << ICE_AQC_RX_EQU_SHIFT)
+#define ICE_AQC_RX_EQU_DRATE (0x15 << ICE_AQC_RX_EQU_SHIFT)
+#define ICE_AQC_TX_EQU_PRE1 0x0
+#define ICE_AQC_TX_EQU_PRE3 0x3
+#define ICE_AQC_TX_EQU_ATTEN 0x4
+#define ICE_AQC_TX_EQU_POST1 0x8
+#define ICE_AQC_TX_EQU_PRE2 0xC
+ __le16 op_code_serdes_sel;
+#define ICE_AQC_OP_CODE_SHIFT 4
+#define ICE_AQC_OP_CODE_RX_EQU (0x9 << ICE_AQC_OP_CODE_SHIFT)
+#define ICE_AQC_OP_CODE_TX_EQU (0x10 << ICE_AQC_OP_CODE_SHIFT)
+ __le32 reserved[3];
+};
+
+struct ice_aqc_dnl_equa_resp {
+ /* Equalization value can be -ve */
+ int val;
+ __le32 reserved[3];
+};
+
/* DNL call command/response buffer (indirect 0x0682) */
struct ice_aqc_dnl_call {
- __le32 stores[4];
+ union {
+ struct ice_aqc_dnl_equa_param txrx_equa_reqs;
+ __le32 stores[4];
+ struct ice_aqc_dnl_equa_resp txrx_equa_resp;
+ } sto;
};
/* Used for both commands:
@@ -1902,8 +1978,8 @@ struct ice_aqc_link_topo_addr {
#define ICE_AQC_LINK_TOPO_HANDLE_M (0x3FF << ICE_AQC_LINK_TOPO_HANDLE_S)
/* Used to decode the handle field */
#define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_M BIT(9)
-#define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_LOM BIT(9)
-#define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_MEZZ 0
+#define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_LOM 0
+#define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_MEZZ BIT(9)
#define ICE_AQC_LINK_TOPO_HANDLE_NODE_S 0
/* In case of a Mezzanine type */
#define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_NODE_M \
@@ -1919,7 +1995,7 @@ struct ice_aqc_link_topo_addr {
struct ice_aqc_get_link_topo {
struct ice_aqc_link_topo_addr addr;
u8 node_part_num;
-#define ICE_ACQ_GET_LINK_TOPO_NODE_NR_PCA9575 0x21
+#define ICE_AQC_GET_LINK_TOPO_NODE_NR_PCA9575 0x21
u8 rsvd[9];
};
@@ -2054,6 +2130,7 @@ struct ice_aqc_get_port_options_elem {
#define ICE_AQC_PORT_OPT_MAX_LANE_25G 5
#define ICE_AQC_PORT_OPT_MAX_LANE_50G 6
#define ICE_AQC_PORT_OPT_MAX_LANE_100G 7
+#define ICE_AQC_PORT_OPT_MAX_LANE_200G 8
u8 global_scid[2];
u8 phy_scid[2];
u8 pf2port_cid[2];
@@ -2201,6 +2278,29 @@ struct ice_aqc_nvm {
#define ICE_AQC_NVM_LLDP_STATUS_M_LEN 4 /* In Bits */
#define ICE_AQC_NVM_LLDP_STATUS_RD_LEN 4 /* In Bytes */
+#define ICE_AQC_NVM_SDP_CFG_PTR_OFFSET 0xD8
+#define ICE_AQC_NVM_SDP_CFG_PTR_RD_LEN 2 /* In Bytes */
+#define ICE_AQC_NVM_SDP_CFG_PTR_M MAKEMASK(0x7FFF, 0)
+#define ICE_AQC_NVM_SDP_CFG_PTR_TYPE_M BIT(15)
+#define ICE_AQC_NVM_SDP_CFG_HEADER_LEN 2 /* In Bytes */
+#define ICE_AQC_NVM_SDP_CFG_SEC_LEN_LEN 2 /* In Bytes */
+#define ICE_AQC_NVM_SDP_CFG_DATA_LEN 14 /* In Bytes */
+#define ICE_AQC_NVM_SDP_CFG_MAX_SECTION_SIZE 7
+#define ICE_AQC_NVM_SDP_CFG_PIN_SIZE 10
+#define ICE_AQC_NVM_SDP_CFG_PIN_OFFSET 6
+#define ICE_AQC_NVM_SDP_CFG_PIN_MASK MAKEMASK(0x3FF, \
+ ICE_AQC_NVM_SDP_CFG_PIN_OFFSET)
+#define ICE_AQC_NVM_SDP_CFG_CHAN_OFFSET 4
+#define ICE_AQC_NVM_SDP_CFG_CHAN_MASK MAKEMASK(0x3, \
+ ICE_AQC_NVM_SDP_CFG_CHAN_OFFSET)
+#define ICE_AQC_NVM_SDP_CFG_DIR_OFFSET 3
+#define ICE_AQC_NVM_SDP_CFG_DIR_MASK MAKEMASK(0x1, \
+ ICE_AQC_NVM_SDP_CFG_DIR_OFFSET)
+#define ICE_AQC_NVM_SDP_CFG_SDP_NUM_OFFSET 0
+#define ICE_AQC_NVM_SDP_CFG_SDP_NUM_MASK MAKEMASK(0x7, \
+ ICE_AQC_NVM_SDP_CFG_SDP_NUM_OFFSET)
+#define ICE_AQC_NVM_SDP_CFG_NA_PIN_MASK MAKEMASK(0x1, 15)
+
#define ICE_AQC_NVM_MINSREV_MOD_ID 0x130
#define ICE_AQC_NVM_TX_TOPO_MOD_ID 0x14B
#define ICE_AQC_NVM_CMPO_MOD_ID 0x153
@@ -2265,6 +2365,29 @@ struct ice_aqc_nvm_checksum {
u8 rsvd2[12];
};
+/* Used for NVM Sanitization command - 0x070C */
+struct ice_aqc_nvm_sanitization {
+ u8 cmd_flags;
+#define ICE_AQ_NVM_SANITIZE_REQ_READ 0
+#define ICE_AQ_NVM_SANITIZE_REQ_OPERATE BIT(0)
+
+#define ICE_AQ_NVM_SANITIZE_READ_SUBJECT_NVM_BITS 0
+#define ICE_AQ_NVM_SANITIZE_READ_SUBJECT_NVM_STATE BIT(1)
+#define ICE_AQ_NVM_SANITIZE_OPERATE_SUBJECT_CLEAR 0
+ u8 values;
+#define ICE_AQ_NVM_SANITIZE_NVM_BITS_HOST_CLEAN_SUPPORT BIT(0)
+#define ICE_AQ_NVM_SANITIZE_NVM_BITS_BMC_CLEAN_SUPPORT BIT(2)
+#define ICE_AQ_NVM_SANITIZE_NVM_STATE_HOST_CLEAN_DONE BIT(0)
+#define ICE_AQ_NVM_SANITIZE_NVM_STATE_HOST_CLEAN_SUCCESS BIT(1)
+#define ICE_AQ_NVM_SANITIZE_NVM_STATE_BMC_CLEAN_DONE BIT(2)
+#define ICE_AQ_NVM_SANITIZE_NVM_STATE_BMC_CLEAN_SUCCESS BIT(3)
+#define ICE_AQ_NVM_SANITIZE_OPERATE_HOST_CLEAN_DONE BIT(0)
+#define ICE_AQ_NVM_SANITIZE_OPERATE_HOST_CLEAN_SUCCESS BIT(1)
+#define ICE_AQ_NVM_SANITIZE_OPERATE_BMC_CLEAN_DONE BIT(2)
+#define ICE_AQ_NVM_SANITIZE_OPERATE_BMC_CLEAN_SUCCESS BIT(3)
+ u8 reserved[14];
+};
+
/*
* Send to PF command (indirect 0x0801) ID is only used by PF
*
@@ -2560,6 +2683,15 @@ struct ice_aqc_get_set_rss_lut {
__le32 addr_low;
};
+/* Sideband Control Interface Commands */
+/* Neighbor Device Request (indirect 0x0C00); also used for the response. */
+struct ice_aqc_neigh_dev_req {
+ __le16 sb_data_len;
+ u8 reserved[6];
+ __le32 addr_high;
+ __le32 addr_low;
+};
+
/* Add Tx LAN Queues (indirect 0x0C30) */
struct ice_aqc_add_txqs {
u8 num_qgrps;
@@ -2812,19 +2944,33 @@ struct ice_aqc_event_lan_overflow {
/* Debug Dump Internal Data (indirect 0xFF08) */
struct ice_aqc_debug_dump_internals {
__le16 cluster_id; /* Expresses next cluster ID in response */
-#define ICE_AQC_DBG_DUMP_CLUSTER_ID_SW 0
-#define ICE_AQC_DBG_DUMP_CLUSTER_ID_TXSCHED 2
-#define ICE_AQC_DBG_DUMP_CLUSTER_ID_PROFILES 3
+#define ICE_AQC_DBG_DUMP_CLUSTER_ID_SW_E810 0
+#define ICE_AQC_DBG_DUMP_CLUSTER_ID_ACL_E810 1
+#define ICE_AQC_DBG_DUMP_CLUSTER_ID_TXSCHED_E810 2
+#define ICE_AQC_DBG_DUMP_CLUSTER_ID_PROFILES_E810 3
/* EMP_DRAM only dumpable in device debug mode */
-#define ICE_AQC_DBG_DUMP_CLUSTER_ID_EMP_DRAM 4
-#define ICE_AQC_DBG_DUMP_CLUSTER_ID_LINK 5
+#define ICE_AQC_DBG_DUMP_CLUSTER_ID_EMP_DRAM_E810 4
+#define ICE_AQC_DBG_DUMP_CLUSTER_ID_LINK_E810 5
/* AUX_REGS only dumpable in device debug mode */
-#define ICE_AQC_DBG_DUMP_CLUSTER_ID_AUX_REGS 6
-#define ICE_AQC_DBG_DUMP_CLUSTER_ID_DCB 7
-#define ICE_AQC_DBG_DUMP_CLUSTER_ID_L2P 8
-#define ICE_AQC_DBG_DUMP_CLUSTER_ID_QUEUE_MNG 9
-#define ICE_AQC_DBG_DUMP_CLUSTER_ID_FULL_CSR_SPACE 21
-#define ICE_AQC_DBG_DUMP_CLUSTER_ID_MNG_TRANSACTIONS 22
+#define ICE_AQC_DBG_DUMP_CLUSTER_ID_AUX_REGS_E810 6
+#define ICE_AQC_DBG_DUMP_CLUSTER_ID_DCB_E810 7
+#define ICE_AQC_DBG_DUMP_CLUSTER_ID_L2P_E810 8
+#define ICE_AQC_DBG_DUMP_CLUSTER_ID_QUEUE_MNG_E810 9
+#define ICE_AQC_DBG_DUMP_CLUSTER_ID_FULL_CSR_SPACE_E810 21
+#define ICE_AQC_DBG_DUMP_CLUSTER_ID_MNG_TRANSACTIONS_E810 22
+
+/* Start cluster to discover first available cluster */
+#define ICE_AQC_DBG_DUMP_CLUSTER_ID_START_ALL 0
+#define ICE_AQC_DBG_DUMP_CLUSTER_ID_SW_E830 100
+#define ICE_AQC_DBG_DUMP_CLUSTER_ID_ACL_E830 101
+#define ICE_AQC_DBG_DUMP_CLUSTER_ID_TXSCHED_E830 102
+#define ICE_AQC_DBG_DUMP_CLUSTER_ID_PROFILES_E830 103
+/* EMP_DRAM only dumpable in device debug mode */
+#define ICE_AQC_DBG_DUMP_CLUSTER_ID_LINK_E830 105
+#define ICE_AQC_DBG_DUMP_CLUSTER_ID_DCB_E830 107
+#define ICE_AQC_DBG_DUMP_CLUSTER_ID_L2P_E830 108
+#define ICE_AQC_DBG_DUMP_CLUSTER_ID_QUEUE_MNG_E830 109
+#define ICE_AQC_DBG_DUMP_CLUSTER_ID_FULL_CSR_SPACE_E830 121
__le16 table_id; /* Used only for non-memory clusters */
__le32 idx; /* In table entries for tables, in bytes for memory */
__le32 addr_high;
@@ -3076,6 +3222,7 @@ struct ice_aq_desc {
struct ice_aqc_nvm nvm;
struct ice_aqc_nvm_cfg nvm_cfg;
struct ice_aqc_nvm_checksum nvm_checksum;
+ struct ice_aqc_nvm_sanitization sanitization;
struct ice_aqc_pf_vf_msg virt;
struct ice_aqc_read_write_alt_direct read_write_alt_direct;
struct ice_aqc_read_write_alt_indirect read_write_alt_indirect;
@@ -3095,6 +3242,7 @@ struct ice_aq_desc {
struct ice_aqc_lldp_filter_ctrl lldp_filter_ctrl;
struct ice_aqc_get_set_rss_lut get_set_rss_lut;
struct ice_aqc_get_set_rss_key get_set_rss_key;
+ struct ice_aqc_neigh_dev_req neigh_dev;
struct ice_aqc_add_txqs add_txqs;
struct ice_aqc_dis_txqs dis_txqs;
struct ice_aqc_move_txqs move_txqs;
@@ -3330,6 +3478,7 @@ enum ice_adminq_opc {
ice_aqc_opc_nvm_update_empr = 0x0709,
ice_aqc_opc_nvm_pkg_data = 0x070A,
ice_aqc_opc_nvm_pass_component_tbl = 0x070B,
+ ice_aqc_opc_nvm_sanitization = 0x070C,
/* PF/VF mailbox commands */
ice_mbx_opc_send_msg_to_pf = 0x0801,
@@ -3360,6 +3509,8 @@ enum ice_adminq_opc {
ice_aqc_opc_set_rss_lut = 0x0B03,
ice_aqc_opc_get_rss_key = 0x0B04,
ice_aqc_opc_get_rss_lut = 0x0B05,
+ /* Sideband Control Interface commands */
+ ice_aqc_opc_neighbour_device_request = 0x0C00,
/* Tx queue handling commands/events */
ice_aqc_opc_add_txqs = 0x0C30,
diff --git a/sys/dev/ice/ice_bitops.h b/sys/dev/ice/ice_bitops.h
index 499ee41228c3..c480900596f4 100644
--- a/sys/dev/ice/ice_bitops.h
+++ b/sys/dev/ice/ice_bitops.h
@@ -445,10 +445,10 @@ ice_bitmap_set(ice_bitmap_t *dst, u16 pos, u16 num_bits)
* Note that this function assumes it is operating on a bitmap declared using
* ice_declare_bitmap.
*/
-static inline int
+static inline u16
ice_bitmap_hweight(ice_bitmap_t *bm, u16 size)
{
- int count = 0;
+ u16 count = 0;
u16 bit = 0;
while (size > (bit = ice_find_next_bit(bm, size, bit))) {
diff --git a/sys/dev/ice/ice_common.c b/sys/dev/ice/ice_common.c
index ef487bcfd0f4..ad4ea4c8e7a1 100644
--- a/sys/dev/ice/ice_common.c
+++ b/sys/dev/ice/ice_common.c
@@ -32,7 +32,6 @@
#include "ice_common.h"
#include "ice_sched.h"
#include "ice_adminq_cmd.h"
-
#include "ice_flow.h"
#include "ice_switch.h"
@@ -111,6 +110,17 @@ static const char * const ice_link_mode_str_high[] = {
ice_arr_elem_idx(2, "100G_CAUI2"),
ice_arr_elem_idx(3, "100G_AUI2_AOC_ACC"),
ice_arr_elem_idx(4, "100G_AUI2"),
+ ice_arr_elem_idx(5, "200G_CR4_PAM4"),
+ ice_arr_elem_idx(6, "200G_SR4"),
+ ice_arr_elem_idx(7, "200G_FR4"),
+ ice_arr_elem_idx(8, "200G_LR4"),
+ ice_arr_elem_idx(9, "200G_DR4"),
+ ice_arr_elem_idx(10, "200G_KR4_PAM4"),
+ ice_arr_elem_idx(11, "200G_AUI4_AOC_ACC"),
+ ice_arr_elem_idx(12, "200G_AUI4"),
+ ice_arr_elem_idx(13, "200G_AUI8_AOC_ACC"),
+ ice_arr_elem_idx(14, "200G_AUI8"),
+ ice_arr_elem_idx(15, "400GBASE_FR8"),
};
/**
@@ -151,7 +161,7 @@ ice_dump_phy_type(struct ice_hw *hw, u64 low, u64 high,
const char *prefix)
* This function sets the MAC type of the adapter based on the
* vendor ID and device ID stored in the HW structure.
*/
-enum ice_status ice_set_mac_type(struct ice_hw *hw)
+int ice_set_mac_type(struct ice_hw *hw)
{
ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
@@ -188,13 +198,43 @@ enum ice_status ice_set_mac_type(struct ice_hw *hw)
case ICE_DEV_ID_E823C_SGMII:
hw->mac_type = ICE_MAC_GENERIC;
break;
+ case ICE_DEV_ID_E825C_BACKPLANE:
+ case ICE_DEV_ID_E825C_QSFP:
+ case ICE_DEV_ID_E825C_SFP:
+ case ICE_DEV_ID_E825C_SGMII:
+ hw->mac_type = ICE_MAC_GENERIC_3K_E825;
+ break;
+ case ICE_DEV_ID_E830_BACKPLANE:
+ case ICE_DEV_ID_E830_QSFP56:
+ case ICE_DEV_ID_E830_SFP:
+ case ICE_DEV_ID_E830C_BACKPLANE:
+ case ICE_DEV_ID_E830_L_BACKPLANE:
+ case ICE_DEV_ID_E830C_QSFP:
+ case ICE_DEV_ID_E830_L_QSFP:
+ case ICE_DEV_ID_E830C_SFP:
+ case ICE_DEV_ID_E830_L_SFP:
+ hw->mac_type = ICE_MAC_E830;
+ break;
default:
hw->mac_type = ICE_MAC_UNKNOWN;
break;
}
ice_debug(hw, ICE_DBG_INIT, "mac_type: %d\n", hw->mac_type);
- return ICE_SUCCESS;
+ return 0;
+}
+
+/**
+ * ice_is_generic_mac
+ * @hw: pointer to the hardware structure
+ *
+ * returns true if mac_type is ICE_MAC_GENERIC, false if not
+ */
+bool ice_is_generic_mac(struct ice_hw *hw)
+{
+ return (hw->mac_type == ICE_MAC_GENERIC ||
+ hw->mac_type == ICE_MAC_GENERIC_3K ||
+ hw->mac_type == ICE_MAC_GENERIC_3K_E825);
}
/**
@@ -223,7 +263,7 @@ bool ice_is_e810t(struct ice_hw *hw)
case ICE_SUBDEV_ID_E810T2:
case ICE_SUBDEV_ID_E810T3:
case ICE_SUBDEV_ID_E810T4:
- case ICE_SUBDEV_ID_E810T5:
+ case ICE_SUBDEV_ID_E810T6:
case ICE_SUBDEV_ID_E810T7:
return true;
}
@@ -231,8 +271,8 @@ bool ice_is_e810t(struct ice_hw *hw)
case ICE_DEV_ID_E810C_QSFP:
switch (hw->subsystem_device_id) {
case ICE_SUBDEV_ID_E810T2:
+ case ICE_SUBDEV_ID_E810T3:
case ICE_SUBDEV_ID_E810T5:
- case ICE_SUBDEV_ID_E810T6:
return true;
}
break;
@@ -243,6 +283,17 @@ bool ice_is_e810t(struct ice_hw *hw)
return false;
}
+/**
+ * ice_is_e830
+ * @hw: pointer to the hardware structure
+ *
+ * returns true if the device is E830 based, false if not.
+ */
+bool ice_is_e830(struct ice_hw *hw)
+{
+ return hw->mac_type == ICE_MAC_E830;
+}
+
/**
* ice_is_e823
* @hw: pointer to the hardware structure
@@ -268,6 +319,25 @@ bool ice_is_e823(struct ice_hw *hw)
}
}
+/**
+ * ice_is_e825c
+ * @hw: pointer to the hardware structure
+ *
+ * returns true if the device is E825-C based, false if not.
+ */
+bool ice_is_e825c(struct ice_hw *hw)
+{
+ switch (hw->device_id) {
+ case ICE_DEV_ID_E825C_BACKPLANE:
+ case ICE_DEV_ID_E825C_QSFP:
+ case ICE_DEV_ID_E825C_SFP:
+ case ICE_DEV_ID_E825C_SGMII:
+ return true;
+ default:
+ return false;
+ }
+}
+
/**
* ice_clear_pf_cfg - Clear PF configuration
* @hw: pointer to the hardware structure
@@ -275,7 +345,7 @@ bool ice_is_e823(struct ice_hw *hw)
* Clears any existing PF configuration (VSIs, VSI lists, switch rules, port
* configuration, flow director filters, etc.).
*/
-enum ice_status ice_clear_pf_cfg(struct ice_hw *hw)
+int ice_clear_pf_cfg(struct ice_hw *hw)
{
struct ice_aq_desc desc;
@@ -299,14 +369,14 @@ enum ice_status ice_clear_pf_cfg(struct ice_hw *hw)
* ice_discover_dev_caps is expected to be called before this function is
* called.
*/
-enum ice_status
+int
ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size,
struct ice_sq_cd *cd)
{
struct ice_aqc_manage_mac_read_resp *resp;
struct ice_aqc_manage_mac_read *cmd;
struct ice_aq_desc desc;
- enum ice_status status;
+ int status;
u16 flags;
u8 i;
@@ -340,7 +410,7 @@ ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16
buf_size,
ETH_ALEN, ICE_NONDMA_TO_NONDMA);
break;
}
- return ICE_SUCCESS;
+ return 0;
}
/**
@@ -401,16 +471,21 @@ static void ice_set_media_type(struct ice_port_info *pi)
* type is FIBER
*/
else if (ice_phy_maps_to_media(phy_type_low, phy_type_high,
- ICE_MEDIA_OPT_PHY_TYPE_LOW_M, 0) ||
- (phy_type_low & ICE_MEDIA_OPT_PHY_TYPE_LOW_M &&
- phy_type_low & ICE_MEDIA_C2M_PHY_TYPE_LOW_M))
+ ICE_MEDIA_OPT_PHY_TYPE_LOW_M,
+ ICE_MEDIA_OPT_PHY_TYPE_HIGH_M) ||
+ ((phy_type_low & ICE_MEDIA_OPT_PHY_TYPE_LOW_M ||
+ phy_type_high & ICE_MEDIA_OPT_PHY_TYPE_HIGH_M) &&
+ (phy_type_low & ICE_MEDIA_C2M_PHY_TYPE_LOW_M ||
+ phy_type_high & ICE_MEDIA_C2C_PHY_TYPE_HIGH_M)))
*media_type = ICE_MEDIA_FIBER;
/* else if PHY types are only DA, or DA and C2C, then media type DA */
else if (ice_phy_maps_to_media(phy_type_low, phy_type_high,
- ICE_MEDIA_DAC_PHY_TYPE_LOW_M, 0) ||
- (phy_type_low & ICE_MEDIA_DAC_PHY_TYPE_LOW_M &&
- (phy_type_low & ICE_MEDIA_C2C_PHY_TYPE_LOW_M ||
- phy_type_high & ICE_MEDIA_C2C_PHY_TYPE_HIGH_M)))
+ ICE_MEDIA_DAC_PHY_TYPE_LOW_M,
+ ICE_MEDIA_DAC_PHY_TYPE_HIGH_M) ||
+ ((phy_type_low & ICE_MEDIA_DAC_PHY_TYPE_LOW_M ||
+ phy_type_high & ICE_MEDIA_DAC_PHY_TYPE_HIGH_M) &&
+ (phy_type_low & ICE_MEDIA_C2C_PHY_TYPE_LOW_M ||
+ phy_type_high & ICE_MEDIA_C2C_PHY_TYPE_HIGH_M)))
*media_type = ICE_MEDIA_DA;
/* else if PHY types are only C2M or only C2C, then media is AUI */
else if (ice_phy_maps_to_media(phy_type_low, phy_type_high,
@@ -435,7 +510,7 @@ static void ice_set_media_type(struct ice_port_info *pi)
*
* Returns the various PHY capabilities supported on the Port (0x0600)
*/
-enum ice_status
+int
ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode,
struct ice_aqc_get_phy_caps_data *pcaps,
struct ice_sq_cd *cd)
@@ -443,9 +518,9 @@ ice_aq_get_phy_caps(struct ice_port_info *pi, bool
qual_mods, u8 report_mode,
struct ice_aqc_get_phy_caps *cmd;
u16 pcaps_size = sizeof(*pcaps);
struct ice_aq_desc desc;
- enum ice_status status;
const char *prefix;
struct ice_hw *hw;
+ int status;
cmd = &desc.params.get_phy;
@@ -510,7 +585,7 @@ ice_aq_get_phy_caps(struct ice_port_info *pi, bool
qual_mods, u8 report_mode,
ice_debug(hw, ICE_DBG_LINK, "%s: module_type[2] = 0x%x\n", prefix,
pcaps->module_type[2]);
- if (status == ICE_SUCCESS && report_mode ==
ICE_AQC_REPORT_TOPO_CAP_MEDIA) {
+ if (!status && report_mode == ICE_AQC_REPORT_TOPO_CAP_MEDIA) {
pi->phy.phy_type_low = LE64_TO_CPU(pcaps->phy_type_low);
pi->phy.phy_type_high = LE64_TO_CPU(pcaps->phy_type_high);
ice_memcpy(pi->phy.link_info.module_type, &pcaps->module_type,
@@ -525,81 +600,65 @@ ice_aq_get_phy_caps(struct ice_port_info *pi, bool
qual_mods, u8 report_mode,
}
/**
- * ice_aq_get_netlist_node
- * @hw: pointer to the hw struct
- * @cmd: get_link_topo AQ structure
- * @node_part_number: output node part number if node found
- * @node_handle: output node handle parameter if node found
+ * ice_aq_get_phy_equalization - function to read serdes equalizer value from
+ * firmware using admin queue command.
+ * @hw: pointer to the HW struct
+ * @data_in: represents the serdes equalization parameter requested
+ * @op_code: represents the serdes number and flag to represent tx or rx
+ * @serdes_num: represents the serdes number
+ * @output: pointer to the caller-supplied buffer to return serdes equalizer
+ *
+ * Returns 0 on success,
+ * non-zero status on error
*/
-enum ice_status
-ice_aq_get_netlist_node(struct ice_hw *hw, struct ice_aqc_get_link_topo *cmd,
- u8 *node_part_number, u16 *node_handle)
+int ice_aq_get_phy_equalization(struct ice_hw *hw, u16 data_in, u16 op_code,
+ u8 serdes_num, int *output)
{
+ struct ice_aqc_dnl_call_command *cmd;
+ struct ice_aqc_dnl_call buf;
struct ice_aq_desc desc;
+ int err = 0;
- ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo);
- desc.params.get_link_topo = *cmd;
+ if (!hw || !output)
+ return (ICE_ERR_PARAM);
- if (ice_aq_send_cmd(hw, &desc, NULL, 0, NULL))
- return ICE_ERR_NOT_SUPPORTED;
+ memset(&buf, 0, sizeof(buf));
+ buf.sto.txrx_equa_reqs.data_in = CPU_TO_LE16(data_in);
+ buf.sto.txrx_equa_reqs.op_code_serdes_sel =
+ CPU_TO_LE16(op_code | (serdes_num & 0xF));
- if (node_handle)
- *node_handle =
- LE16_TO_CPU(desc.params.get_link_topo.addr.handle);
- if (node_part_number)
- *node_part_number = desc.params.get_link_topo.node_part_num;
+ cmd = &desc.params.dnl_call;
+ ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dnl_call);
+ desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_BUF | ICE_AQ_FLAG_RD |
+ ICE_AQ_FLAG_SI);
+ desc.datalen = CPU_TO_LE16(sizeof(struct ice_aqc_dnl_call));
+ cmd->activity_id = CPU_TO_LE16(ICE_AQC_ACT_ID_DNL);
+ cmd->ctx = 0;
- return ICE_SUCCESS;
+ err = ice_aq_send_cmd(hw, &desc, &buf,
+ sizeof(struct ice_aqc_dnl_call), NULL);
+ if (!err)
+ *output = buf.sto.txrx_equa_resp.val;
+
+ return err;
}
-#define MAX_NETLIST_SIZE 10
+#define ice_get_link_status_data_ver(hw) ((hw)->mac_type == ICE_MAC_E830 ? \
+ ICE_GET_LINK_STATUS_DATA_V2 : ICE_GET_LINK_STATUS_DATA_V1)
+
/**
- * ice_find_netlist_node
- * @hw: pointer to the hw struct
- * @node_type_ctx: type of netlist node to look for
- * @node_part_number: node part number to look for
- * @node_handle: output parameter if node found - optional
+ * ice_get_link_status_datalen
+ * @hw: pointer to the HW struct
*
- * Find and return the node handle for a given node type and part number in the
- * netlist. When found ICE_SUCCESS is returned, ICE_ERR_DOES_NOT_EXIST
- * otherwise. If node_handle provided, it would be set to found node handle.
+ * return Get Link Status datalen
*/
-enum ice_status
-ice_find_netlist_node(struct ice_hw *hw, u8 node_type_ctx, u8 node_part_number,
- u16 *node_handle)
+static u16 ice_get_link_status_datalen(struct ice_hw *hw)
{
- struct ice_aqc_get_link_topo cmd;
- u8 rec_node_part_number;
- u16 rec_node_handle;
- u8 idx;
-
- for (idx = 0; idx < MAX_NETLIST_SIZE; idx++) {
- enum ice_status status;
-
- memset(&cmd, 0, sizeof(cmd));
-
- cmd.addr.topo_params.node_type_ctx =
- (node_type_ctx << ICE_AQC_LINK_TOPO_NODE_TYPE_S);
- cmd.addr.topo_params.index = idx;
-
- status = ice_aq_get_netlist_node(hw, &cmd,
- &rec_node_part_number,
- &rec_node_handle);
- if (status)
- return status;
-
- if (rec_node_part_number == node_part_number) {
- if (node_handle)
- *node_handle = rec_node_handle;
- return ICE_SUCCESS;
- }
- }
-
- return ICE_ERR_DOES_NOT_EXIST;
+ return (ice_get_link_status_data_ver(hw) ==
+ ICE_GET_LINK_STATUS_DATA_V1) ? ICE_GET_LINK_STATUS_DATALEN_V1 :
+ ICE_GET_LINK_STATUS_DATALEN_V2;
}
-#define ice_get_link_status_datalen(hw) ICE_GET_LINK_STATUS_DATALEN_V1
-
/**
* ice_aq_get_link_info
* @pi: port information structure
@@ -609,7 +668,7 @@ ice_find_netlist_node(struct ice_hw *hw, u8 node_type_ctx,
u8 node_part_number,
*
* Get Link Status (0x607). Returns the link status of the adapter.
*/
-enum ice_status
+int
ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse,
struct ice_link_status *link, struct ice_sq_cd *cd)
{
@@ -619,9 +678,9 @@ ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse,
struct ice_fc_info *hw_fc_info;
bool tx_pause, rx_pause;
struct ice_aq_desc desc;
- enum ice_status status;
struct ice_hw *hw;
u16 cmd_flags;
+ int status;
if (!pi)
return ICE_ERR_PARAM;
@@ -639,7 +698,7 @@ ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse,
status = ice_aq_send_cmd(hw, &desc, &link_data,
ice_get_link_status_datalen(hw), cd);
- if (status != ICE_SUCCESS)
+ if (status)
return status;
/* save off old link status information */
@@ -696,7 +755,7 @@ ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse,
/* flag cleared so calling functions don't call AQ again */
pi->phy.get_link_info = false;
- return ICE_SUCCESS;
+ return 0;
}
/**
@@ -721,17 +780,28 @@ ice_fill_tx_timer_and_fc_thresh(struct ice_hw *hw,
* Also, because we are operating on transmit timer and fc
* threshold of LFC, we don't turn on any bit in tx_tmr_priority
*/
-#define IDX_OF_LFC PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX
+#define E800_IDX_OF_LFC E800_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX
- /* Retrieve the transmit timer */
- val = rd32(hw, PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(IDX_OF_LFC));
- tx_timer_val = val &
- PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_M;
- cmd->tx_tmr_value = CPU_TO_LE16(tx_timer_val);
+ if ((hw)->mac_type == ICE_MAC_E830) {
+ /* Retrieve the transmit timer */
+ val = rd32(hw, E830_PRTMAC_CL01_PAUSE_QUANTA);
+ tx_timer_val = val &
E830_PRTMAC_CL01_PAUSE_QUANTA_CL0_PAUSE_QUANTA_M;
+ cmd->tx_tmr_value = CPU_TO_LE16(tx_timer_val);
- /* Retrieve the fc threshold */
- val = rd32(hw, PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(IDX_OF_LFC));
- fc_thres_val = val & PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_M;
+ /* Retrieve the fc threshold */
+ val = rd32(hw, E830_PRTMAC_CL01_QUANTA_THRESH);
+ fc_thres_val = val &
E830_PRTMAC_CL01_QUANTA_THRESH_CL0_QUANTA_THRESH_M;
+ } else {
+ /* Retrieve the transmit timer */
+ val = rd32(hw,
E800_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(E800_IDX_OF_LFC));
+ tx_timer_val = val &
+
E800_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_M;
+ cmd->tx_tmr_value = CPU_TO_LE16(tx_timer_val);
+
+ /* Retrieve the fc threshold */
+ val = rd32(hw,
E800_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(E800_IDX_OF_LFC));
+ fc_thres_val = val &
E800_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_M;
+ }
cmd->fc_refresh_threshold = CPU_TO_LE16(fc_thres_val);
}
@@ -745,7 +815,7 @@ ice_fill_tx_timer_and_fc_thresh(struct ice_hw *hw,
*
* Set MAC configuration (0x0603)
*/
-enum ice_status
+int
ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, bool auto_drop,
struct ice_sq_cd *cd)
{
@@ -772,10 +842,10 @@ ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size,
bool auto_drop,
* ice_init_fltr_mgmt_struct - initializes filter management list and locks
* @hw: pointer to the HW struct
*/
-static enum ice_status ice_init_fltr_mgmt_struct(struct ice_hw *hw)
+int ice_init_fltr_mgmt_struct(struct ice_hw *hw)
{
struct ice_switch_info *sw;
- enum ice_status status;
+ int status;
hw->switch_info = (struct ice_switch_info *)
ice_malloc(hw, sizeof(*hw->switch_info));
@@ -793,7 +863,7 @@ static enum ice_status ice_init_fltr_mgmt_struct(struct
ice_hw *hw)
ice_free(hw, hw->switch_info);
return status;
}
- return ICE_SUCCESS;
+ return 0;
}
/**
@@ -866,7 +936,7 @@ ice_cleanup_fltr_mgmt_single(struct ice_hw *hw, struct
ice_switch_info *sw)
* ice_cleanup_fltr_mgmt_struct - cleanup filter management list and locks
* @hw: pointer to the HW struct
*/
-static void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw)
+void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw)
{
ice_cleanup_fltr_mgmt_single(hw, hw->switch_info);
}
@@ -911,7 +981,7 @@ void ice_print_rollback_msg(struct ice_hw *hw)
orom = &hw->flash.orom;
nvm = &hw->flash.nvm;
- SNPRINTF(nvm_str, sizeof(nvm_str), "%x.%02x 0x%x %d.%d.%d",
+ (void)SNPRINTF(nvm_str, sizeof(nvm_str), "%x.%02x 0x%x %d.%d.%d",
nvm->major, nvm->minor, nvm->eetrack, orom->major,
orom->build, orom->patch);
ice_warn(hw,
@@ -934,12 +1004,12 @@ void ice_set_umac_shared(struct ice_hw *hw)
* ice_init_hw - main hardware initialization routine
* @hw: pointer to the hardware structure
*/
-enum ice_status ice_init_hw(struct ice_hw *hw)
+int ice_init_hw(struct ice_hw *hw)
{
struct ice_aqc_get_phy_caps_data *pcaps;
- enum ice_status status;
u16 mac_buf_len;
void *mac_buf;
+ int status;
ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
@@ -957,6 +1027,8 @@ enum ice_status ice_init_hw(struct ice_hw *hw)
return status;
ice_get_itr_intrl_gran(hw);
+ hw->fw_vsi_num = ICE_DFLT_VSI_INVAL;
+
status = ice_create_all_ctrlq(hw);
if (status)
goto err_unroll_cqinit;
@@ -987,9 +1059,11 @@ enum ice_status ice_init_hw(struct ice_hw *hw)
if (ice_get_fw_mode(hw) == ICE_FW_MODE_ROLLBACK)
ice_print_rollback_msg(hw);
- status = ice_clear_pf_cfg(hw);
- if (status)
- goto err_unroll_cqinit;
+ if (!hw->skip_clear_pf) {
+ status = ice_clear_pf_cfg(hw);
+ if (status)
+ goto err_unroll_cqinit;
+ }
ice_clear_pxe_mode(hw);
@@ -1005,6 +1079,8 @@ enum ice_status ice_init_hw(struct ice_hw *hw)
goto err_unroll_cqinit;
}
+ hw->port_info->loopback_mode =
ICE_AQC_SET_P_PARAMS_LOOPBACK_MODE_NORMAL;
+
/* set the back pointer to HW */
hw->port_info->hw = hw;
@@ -1088,7 +1164,7 @@ enum ice_status ice_init_hw(struct ice_hw *hw)
goto err_unroll_fltr_mgmt_struct;
ice_init_lock(&hw->tnl_lock);
- return ICE_SUCCESS;
+ return 0;
err_unroll_fltr_mgmt_struct:
ice_cleanup_fltr_mgmt_struct(hw);
@@ -1135,7 +1211,7 @@ void ice_deinit_hw(struct ice_hw *hw)
* ice_check_reset - Check to see if a global reset is complete
* @hw: pointer to the hardware structure
*/
-enum ice_status ice_check_reset(struct ice_hw *hw)
+int ice_check_reset(struct ice_hw *hw)
{
u32 cnt, reg = 0, grst_timeout, uld_mask, reset_wait_cnt;
*** 16783 LINES SKIPPED ***
