The branch main has been updated by andrew: URL: https://cgit.FreeBSD.org/src/commit/?id=7823d306d3b29b3be5fd74b610241c6307fc9e82
commit 7823d306d3b29b3be5fd74b610241c6307fc9e82 Author: Andrew Turner <[email protected]> AuthorDate: 2026-05-13 10:27:19 +0000 Commit: Andrew Turner <[email protected]> CommitDate: 2026-08-26 11:17:17 +0000 arm64: vmm: Move vgic_v3 structures to header file Move vgic_v3 structures in preparation for vgic interface rework for GICv5 support. Reviewed by: Sarah Walker <[email protected]> Sponsored by: Arm Ltd --- sys/arm64/vmm/io/vgic_internal.h | 83 ++++++++++++++++++++++++++++++++++++++++ sys/arm64/vmm/io/vgic_v3.c | 53 ++----------------------- 2 files changed, 87 insertions(+), 49 deletions(-) diff --git a/sys/arm64/vmm/io/vgic_internal.h b/sys/arm64/vmm/io/vgic_internal.h new file mode 100644 index 000000000000..2f5cfc7c0891 --- /dev/null +++ b/sys/arm64/vmm/io/vgic_internal.h @@ -0,0 +1,83 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (C) 2018 Alexandru Elisei <[email protected]> + * Copyright (C) 2020-2022 Andrew Turner + * Copyright (C) 2023 Arm Ltd + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _VGIC_INTERNAL_H_ +#define _VGIC_INTERNAL_H_ + +struct vgic_v3_irq { + /* List of IRQs that are active or pending */ + TAILQ_ENTRY(vgic_v3_irq) act_pend_list; + struct mtx irq_spinmtx; + uint64_t mpidr; + int target_vcpu; + uint32_t irq; + bool active; + bool pending; + bool enabled; + bool level; + bool on_aplist; + uint8_t priority; + uint8_t config; +#define VGIC_CONFIG_MASK 0x2 +#define VGIC_CONFIG_LEVEL 0x0 +#define VGIC_CONFIG_EDGE 0x2 +}; + +/* Global data not needed by EL2 */ +struct vgic_v3 { + struct mtx dist_mtx; + uint64_t dist_start; + size_t dist_end; + + uint64_t redist_start; + size_t redist_end; + + uint32_t gicd_ctlr; /* Distributor Control Register */ + + struct vgic_v3_irq *irqs; +}; + +/* Per-CPU data not needed by EL2 */ +struct vgic_v3_cpu { + /* + * We need a mutex for accessing the list registers because they are + * modified asynchronously by the virtual timer. + * + * Note that the mutex *MUST* be a spin mutex because an interrupt can + * be injected by a callout callback function, thereby modifying the + * list registers from a context where sleeping is forbidden. + */ + struct mtx lr_mtx; + + struct vgic_v3_irq *private_irqs; + TAILQ_HEAD(, vgic_v3_irq) irq_act_pend; + u_int ich_lr_used; +}; + +#endif /* _VGIC_INTERNAL_H_ */ diff --git a/sys/arm64/vmm/io/vgic_v3.c b/sys/arm64/vmm/io/vgic_v3.c index 09d1448c1803..763267a2a3c8 100644 --- a/sys/arm64/vmm/io/vgic_v3.c +++ b/sys/arm64/vmm/io/vgic_v3.c @@ -72,6 +72,7 @@ #include <dev/vmm/vmm_vm.h> #include "vgic.h" +#include "vgic_internal.h" #include "vgic_v3.h" #include "vgic_v3_reg.h" @@ -92,55 +93,6 @@ struct vgic_v3_virt_features { size_t ich_apr_num; }; -struct vgic_v3_irq { - /* List of IRQs that are active or pending */ - TAILQ_ENTRY(vgic_v3_irq) act_pend_list; - struct mtx irq_spinmtx; - uint64_t mpidr; - int target_vcpu; - uint32_t irq; - bool active; - bool pending; - bool enabled; - bool level; - bool on_aplist; - uint8_t priority; - uint8_t config; -#define VGIC_CONFIG_MASK 0x2 -#define VGIC_CONFIG_LEVEL 0x0 -#define VGIC_CONFIG_EDGE 0x2 -}; - -/* Global data not needed by EL2 */ -struct vgic_v3 { - struct mtx dist_mtx; - uint64_t dist_start; - size_t dist_end; - - uint64_t redist_start; - size_t redist_end; - - uint32_t gicd_ctlr; /* Distributor Control Register */ - - struct vgic_v3_irq *irqs; -}; - -/* Per-CPU data not needed by EL2 */ -struct vgic_v3_cpu { - /* - * We need a mutex for accessing the list registers because they are - * modified asynchronously by the virtual timer. - * - * Note that the mutex *MUST* be a spin mutex because an interrupt can - * be injected by a callout callback function, thereby modifying the - * list registers from a context where sleeping is forbidden. - */ - struct mtx lr_mtx; - - struct vgic_v3_irq private_irqs[VGIC_PRV_I_NUM]; - TAILQ_HEAD(, vgic_v3_irq) irq_act_pend; - u_int ich_lr_used; -}; /* How many IRQs we support (SGIs + PPIs + SPIs). Not including LPIs */ #define VGIC_NIRQS 1023 @@ -474,6 +426,9 @@ vgic_v3_cpuinit(device_t dev, struct hypctx *hypctx) mtx_init(&vgic_cpu->lr_mtx, "VGICv3 ICH_LR_EL2 lock", NULL, MTX_SPIN); + vgic_cpu->private_irqs = mallocarray(VGIC_PRV_I_NUM, + sizeof(*vgic_cpu->private_irqs), M_VGIC_V3, M_WAITOK | M_ZERO); + /* Set the SGI and PPI state */ for (irqid = 0; irqid < VGIC_PRV_I_NUM; irqid++) { irq = &vgic_cpu->private_irqs[irqid];
