The branch main has been updated by jhibbits: URL: https://cgit.FreeBSD.org/src/commit/?id=42f9049ab8d69900b395381d72101ab703b9fe87
commit 42f9049ab8d69900b395381d72101ab703b9fe87 Author: Justin Hibbits <[email protected]> AuthorDate: 2026-09-05 04:09:07 +0000 Commit: Justin Hibbits <[email protected]> CommitDate: 2026-09-05 04:09:07 +0000 powerpc/watchdog: Make e500 watchdog action tunable There are 4 options for e500 watchdog timeout, which may be core- or even SoC- specific. Add support to tune the behavior via a tunable (machdep.watchdog_mode). The tunable value is an integer 0-3. --- sys/powerpc/booke/machdep_e500.c | 9 +++++++-- sys/powerpc/include/spr.h | 1 + 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/sys/powerpc/booke/machdep_e500.c b/sys/powerpc/booke/machdep_e500.c index 2f39a66aac6d..92e0f8387865 100644 --- a/sys/powerpc/booke/machdep_e500.c +++ b/sys/powerpc/booke/machdep_e500.c @@ -148,6 +148,10 @@ cpu_machine_check(struct thread *td, struct trapframe *frame, int *ucode) * * With all PowerPC numbering, 0 is the MSB, and 63 is LSB. */ +/* Default watchdog_mode to chip reset (2). */ +static int watchdog_mode = (TCR_WRC_CHIP >> TCR_WRC_SHIFT); + +TUNABLE_INT("machdep.watchdog_mode", &watchdog_mode); /* Arg is the timebase bit number 1-based (flsll result) */ static void booke_watchdog_cpu(void *arg) @@ -162,7 +166,8 @@ booke_watchdog_cpu(void *arg) tcr &= ~(TCR_WP_MASK | TCR_WPEXT_MASK); tcr |= TCR_MAKE_WP(bitno); - tcr |= TCR_WRC_CHIP | TCR_WIE; + tcr |= ((watchdog_mode << TCR_WRC_SHIFT) & TCR_WRC_MASK); + tcr |= TCR_WIE; mtspr(SPR_TCR, tcr); } @@ -190,7 +195,7 @@ booke_watchdog_fn(void *priv, sbintime_t sbt, sbintime_t *esbt, int *err) * count, using only a mask of the current timebase matching the tick * size. This will give us the next rollover bit *beyond* the timeout. */ - tb = mftb() & ((1 << flsll(ticks)) - 1); + tb = mftb() & ((1ULL << flsll(ticks)) - 1); tb += ticks; tb_bit = 64 - flsll(tb); diff --git a/sys/powerpc/include/spr.h b/sys/powerpc/include/spr.h index 40911a7c293d..2104c08bd296 100644 --- a/sys/powerpc/include/spr.h +++ b/sys/powerpc/include/spr.h @@ -539,6 +539,7 @@ #define TCR_WRC_CORE 0x10000000 /* Core reset */ #define TCR_WRC_CHIP 0x20000000 /* Chip reset */ #define TCR_WRC_SYSTEM 0x30000000 /* System reset */ +#define TCR_WRC_SHIFT 28 #define TCR_WIE 0x08000000 /* Watchdog Interrupt Enable */ #define TCR_PIE 0x04000000 /* PIT Interrupt Enable */ #define TCR_DIE 0x04000000 /* Pecrementer Interrupt Enable */
