The branch main has been updated by andrew: URL: https://cgit.FreeBSD.org/src/commit/?id=747c3779630f7e25ac40ec68c58e24ca3dd5c1ff
commit 747c3779630f7e25ac40ec68c58e24ca3dd5c1ff Author: Andrew Turner <[email protected]> AuthorDate: 2026-09-07 23:28:54 +0000 Commit: Andrew Turner <[email protected]> CommitDate: 2026-09-08 03:05:26 +0000 arm64: Fix the CTR_EL0 field names Use the field names from the Arm Documentation for the CTR_EL0 register. These will later be generated from a BSD Licensed JSON file so to reduce the diff for that rename now. Reviewed by: Kajetan Puchalski <[email protected]> Sponsored by: Arm Ltd Differential Revision: https://reviews.freebsd.org/D59173 --- stand/arm64/libarm64/cache.c | 2 +- sys/arm64/arm64/identcpu.c | 38 +++++++++++++++++++------------------- sys/arm64/include/armreg.h | 32 ++++++++++++++++---------------- sys/arm64/vmm/vmm_nvhe.c | 2 +- 4 files changed, 37 insertions(+), 37 deletions(-) diff --git a/stand/arm64/libarm64/cache.c b/stand/arm64/libarm64/cache.c index 7b74f584ffe3..53e705637d13 100644 --- a/stand/arm64/libarm64/cache.c +++ b/stand/arm64/libarm64/cache.c @@ -68,7 +68,7 @@ get_dcache_line_size(uint64_t ctr) * Relevant field [19:16] is LOG2 * of the number of words in DCache line */ - dcl_size = CTR_DLINE_SIZE(ctr); + dcl_size = CTR_DminLine_SIZE(ctr); /* Size of word shifted by cache line size */ return (sizeof(int) << dcl_size); diff --git a/sys/arm64/arm64/identcpu.c b/sys/arm64/arm64/identcpu.c index 400ea5860695..832357257997 100644 --- a/sys/arm64/arm64/identcpu.c +++ b/sys/arm64/arm64/identcpu.c @@ -475,19 +475,19 @@ static const struct mrs_field_value ctr_erg[] = { }; static const struct mrs_field_value ctr_dline[] = { - MRS_FIELD_VALUE_CACHE(CTR, DLINE, "4 byte D-cacheline", + MRS_FIELD_VALUE_CACHE(CTR, DminLine, "4 byte D-cacheline", "byte D-cacheline"), MRS_FIELD_VALUE_END, }; static const struct mrs_field_value ctr_l1ip[] = { - MRS_FIELD_VALUE(CTR_L1IP_VIPT, "VIPT I-cache"), - MRS_FIELD_VALUE(CTR_L1IP_PIPT, "PIPT I-cache"), + MRS_FIELD_VALUE(CTR_L1Ip_VIPT, "VIPT I-cache"), + MRS_FIELD_VALUE(CTR_L1Ip_PIPT, "PIPT I-cache"), MRS_FIELD_VALUE_END, }; static const struct mrs_field_value ctr_iline[] = { - MRS_FIELD_VALUE_CACHE(CTR, ILINE, "4 byte I-cacheline", + MRS_FIELD_VALUE_CACHE(CTR, IminLine, "4 byte I-cacheline", "byte I-cacheline"), MRS_FIELD_VALUE_END, }; @@ -499,12 +499,12 @@ static const struct mrs_field ctr_fields[] = { MRS_FIELD(CTR, IDC, false, MRS_LOWER, MRS_USERSPACE, ctr_idc), MRS_FIELD(CTR, CWG, false, MRS_HIGHER_OR_ZERO, MRS_USERSPACE, ctr_cwg), MRS_FIELD(CTR, ERG, false, MRS_HIGHER_OR_ZERO, MRS_USERSPACE, ctr_erg), - MRS_FIELD(CTR, DLINE, false, MRS_LOWER, MRS_USERSPACE, ctr_dline), + MRS_FIELD(CTR, DminLine, false, MRS_LOWER, MRS_USERSPACE, ctr_dline), /* If the ICache types are different report the safe option */ - MRS_FIELD(CTR, L1IP, false, MRS_EXACT_IF_DIFFERENT | - MRS_SAFE(CTR_L1IP_VIPT >> CTR_L1IP_SHIFT), MRS_USERSPACE, + MRS_FIELD(CTR, L1Ip, false, MRS_EXACT_IF_DIFFERENT | + MRS_SAFE(CTR_L1Ip_VIPT >> CTR_L1Ip_SHIFT), MRS_USERSPACE, ctr_l1ip), - MRS_FIELD(CTR, ILINE, false, MRS_LOWER, MRS_USERSPACE, ctr_iline), + MRS_FIELD(CTR, IminLine, false, MRS_LOWER, MRS_USERSPACE, ctr_iline), MRS_FIELD_END, }; @@ -2332,7 +2332,7 @@ user_ctr_enable(const struct cpu_feat *feat __unused, if (errata_status != ERRATA_NONE && PCPU_GET(cpuid) == 0 && cpu_feat_has_erratum(errata_list, errata_count, 1542419)) { /* Clear fields we will change */ - user_cpu_desc.ctr &= ~(CTR_DIC_MASK | CTR_ILINE_WIDTH); + user_cpu_desc.ctr &= ~(CTR_DIC_MASK | CTR_IminLine_WIDTH); /* * Set DIC to none so userspace will execute an 'ic ivau' @@ -2346,7 +2346,7 @@ user_ctr_enable(const struct cpu_feat *feat __unused, * 4-byte words the instruction covers. As PAGE_SHIFT is log2 * of the number of bytes in a page we need to subtract 2. */ - user_cpu_desc.ctr |= (PAGE_SHIFT - 2) << CTR_ILINE_SHIFT; + user_cpu_desc.ctr |= (PAGE_SHIFT - 2) << CTR_IminLine_SHIFT; l_user_cpu_desc.ctr = user_cpu_desc.ctr; } @@ -3301,11 +3301,11 @@ identify_cache(uint64_t ctr) { /* Identify the L1 cache type */ - switch (CTR_L1IP_VAL(ctr)) { - case CTR_L1IP_PIPT: + switch (CTR_L1Ip_VAL(ctr)) { + case CTR_L1Ip_PIPT: break; default: - case CTR_L1IP_VIPT: + case CTR_L1Ip_VIPT: icache_aliasing = true; break; } @@ -3315,21 +3315,21 @@ identify_cache(uint64_t ctr) __func__, icache_line_size)); /* Get the D cache line size */ - dcache_line_size = CTR_DLINE_SIZE(ctr); + dcache_line_size = CTR_DminLine_SIZE(ctr); /* And the same for the I cache */ - icache_line_size = CTR_ILINE_SIZE(ctr); + icache_line_size = CTR_IminLine_SIZE(ctr); idcache_line_size = MIN(dcache_line_size, icache_line_size); } - if (dcache_line_size != CTR_DLINE_SIZE(ctr)) { + if (dcache_line_size != CTR_DminLine_SIZE(ctr)) { printf("WARNING: D-cacheline size mismatch %ld != %d\n", - dcache_line_size, CTR_DLINE_SIZE(ctr)); + dcache_line_size, CTR_DminLine_SIZE(ctr)); } - if (icache_line_size != CTR_ILINE_SIZE(ctr)) { + if (icache_line_size != CTR_IminLine_SIZE(ctr)) { printf("WARNING: I-cacheline size mismatch %ld != %d\n", - icache_line_size, CTR_ILINE_SIZE(ctr)); + icache_line_size, CTR_IminLine_SIZE(ctr)); } } diff --git a/sys/arm64/include/armreg.h b/sys/arm64/include/armreg.h index 587c05b39856..779485dfa61c 100644 --- a/sys/arm64/include/armreg.h +++ b/sys/arm64/include/armreg.h @@ -445,22 +445,22 @@ #define CTR_ERG_MASK (0xf << CTR_ERG_SHIFT) #define CTR_ERG_VAL(reg) ((reg) & CTR_ERG_MASK) #define CTR_ERG_SIZE(reg) (4 << (CTR_ERG_VAL(reg) >> CTR_ERG_SHIFT)) -#define CTR_DLINE_SHIFT 16 -#define CTR_DLINE_WIDTH 4 -#define CTR_DLINE_MASK (0xf << CTR_DLINE_SHIFT) -#define CTR_DLINE_VAL(reg) ((reg) & CTR_DLINE_MASK) -#define CTR_DLINE_SIZE(reg) (4 << (CTR_DLINE_VAL(reg) >> CTR_DLINE_SHIFT)) -#define CTR_L1IP_SHIFT 14 -#define CTR_L1IP_WIDTH 2 -#define CTR_L1IP_MASK (0x3 << CTR_L1IP_SHIFT) -#define CTR_L1IP_VAL(reg) ((reg) & CTR_L1IP_MASK) -#define CTR_L1IP_VIPT (2 << CTR_L1IP_SHIFT) -#define CTR_L1IP_PIPT (3 << CTR_L1IP_SHIFT) -#define CTR_ILINE_SHIFT 0 -#define CTR_ILINE_WIDTH 4 -#define CTR_ILINE_MASK (0xf << CTR_ILINE_SHIFT) -#define CTR_ILINE_VAL(reg) ((reg) & CTR_ILINE_MASK) -#define CTR_ILINE_SIZE(reg) (4 << (CTR_ILINE_VAL(reg) >> CTR_ILINE_SHIFT)) +#define CTR_DminLine_SHIFT 16 +#define CTR_DminLine_WIDTH 4 +#define CTR_DminLine_MASK (0xf << CTR_DminLine_SHIFT) +#define CTR_DminLine_VAL(reg) ((reg) & CTR_DminLine_MASK) +#define CTR_DminLine_SIZE(reg) (4 << (CTR_DminLine_VAL(reg) >> CTR_DminLine_SHIFT)) +#define CTR_L1Ip_SHIFT 14 +#define CTR_L1Ip_WIDTH 2 +#define CTR_L1Ip_MASK (0x3 << CTR_L1Ip_SHIFT) +#define CTR_L1Ip_VAL(reg) ((reg) & CTR_L1Ip_MASK) +#define CTR_L1Ip_VIPT (2 << CTR_L1Ip_SHIFT) +#define CTR_L1Ip_PIPT (3 << CTR_L1Ip_SHIFT) +#define CTR_IminLine_SHIFT 0 +#define CTR_IminLine_WIDTH 4 +#define CTR_IminLine_MASK (0xf << CTR_IminLine_SHIFT) +#define CTR_IminLine_VAL(reg) ((reg) & CTR_IminLine_MASK) +#define CTR_IminLine_SIZE(reg) (4 << (CTR_IminLine_VAL(reg) >> CTR_IminLine_SHIFT)) /* CurrentEL - Current Exception Level */ #define CURRENTEL_EL_SHIFT 2 diff --git a/sys/arm64/vmm/vmm_nvhe.c b/sys/arm64/vmm/vmm_nvhe.c index 3d42fc1d5900..59fff2770416 100644 --- a/sys/arm64/vmm/vmm_nvhe.c +++ b/sys/arm64/vmm/vmm_nvhe.c @@ -55,7 +55,7 @@ vmm_dc_civac(uint64_t start, uint64_t len) uint64_t ctr; ctr = READ_SPECIALREG(ctr_el0); - line_size = sizeof(int) << CTR_DLINE_SIZE(ctr); + line_size = sizeof(int) << CTR_DminLine_SIZE(ctr); end = start + len; dsb(ishst); /* Clean and Invalidate the D-cache */
