The branch main has been updated by kbowling (ports committer):
URL:
https://cgit.FreeBSD.org/src/commit/?id=d50f362b505e9026fbd33d00dc43e09cac26a209
commit d50f362b505e9026fbd33d00dc43e09cac26a209
Author: Guinan Sun <guinanx....@intel.com>
AuthorDate: 2020-07-06 08:12:04 +0000
Commit: Kevin Bowling <kbowl...@freebsd.org>
CommitDate: 2021-09-17 21:16:15 +0000
e1000: modify HW level time sync mechanisms
Add additional configuration space access to allow HW
level time sync mechanism.
Signed-off-by: Evgeny Efimov <evgeny.efi...@intel.com>
Signed-off-by: Guinan Sun <guinanx....@intel.com>
Reviewed-by: Wei Zhao <wei.zh...@intel.com>
Approved by: imp
Obtained from: DPDK (d53391f1fe2e0eba8818517fdf285f893d95dcc8)
MFC after: 1 week
---
sys/dev/e1000/e1000_ich8lan.c | 18 ++++++++++++++++++
sys/dev/e1000/e1000_ich8lan.h | 2 ++
2 files changed, 20 insertions(+)
diff --git a/sys/dev/e1000/e1000_ich8lan.c b/sys/dev/e1000/e1000_ich8lan.c
index 3a912dc3870e..1d15881f047d 100644
--- a/sys/dev/e1000/e1000_ich8lan.c
+++ b/sys/dev/e1000/e1000_ich8lan.c
@@ -4963,6 +4963,7 @@ static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
u16 kum_cfg;
u32 ctrl, reg;
s32 ret_val;
+ u16 pci_cfg;
DEBUGFUNC("e1000_reset_hw_ich8lan");
@@ -5023,11 +5024,28 @@ static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
e1000_gate_hw_phy_config_ich8lan(hw, TRUE);
}
ret_val = e1000_acquire_swflag_ich8lan(hw);
+
+ /* Read from EXTCNF_CTRL in e1000_acquire_swflag_ich8lan function
+ * may occur during global reset and cause system hang.
+ * Configuration space access creates the needed delay.
+ * Write to E1000_STRAP RO register E1000_PCI_VENDOR_ID_REGISTER value
+ * insures configuration space read is done before global reset.
+ */
+ e1000_read_pci_cfg(hw, E1000_PCI_VENDOR_ID_REGISTER, &pci_cfg);
+ E1000_WRITE_REG(hw, E1000_STRAP, pci_cfg);
DEBUGOUT("Issuing a global reset to ich8lan\n");
E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_RST));
/* cannot issue a flush here because it hangs the hardware */
msec_delay(20);
+ /* Configuration space access improve HW level time sync mechanism.
+ * Write to E1000_STRAP RO register E1000_PCI_VENDOR_ID_REGISTER
+ * value to insure configuration space read is done
+ * before any access to mac register.
+ */
+ e1000_read_pci_cfg(hw, E1000_PCI_VENDOR_ID_REGISTER, &pci_cfg);
+ E1000_WRITE_REG(hw, E1000_STRAP, pci_cfg);
+
/* Set Phy Config Counter to 50msec */
if (hw->mac.type == e1000_pch2lan) {
reg = E1000_READ_REG(hw, E1000_FEXTNVM3);
diff --git a/sys/dev/e1000/e1000_ich8lan.h b/sys/dev/e1000/e1000_ich8lan.h
index a467e647636f..12f912ebc6e0 100644
--- a/sys/dev/e1000/e1000_ich8lan.h
+++ b/sys/dev/e1000/e1000_ich8lan.h
@@ -327,6 +327,8 @@
#define E1000_SVCR_OFF_TIMER_SHIFT 16
#define E1000_SVT_OFF_HWM_MASK 0x0000001F
+#define E1000_PCI_VENDOR_ID_REGISTER 0x00
+
void e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
bool state);
void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw);
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