The branch main has been updated by mmel: URL: https://cgit.FreeBSD.org/src/commit/?id=7c0ec6638548e78a4fd85a5a2d811bac7c2da98b
commit 7c0ec6638548e78a4fd85a5a2d811bac7c2da98b Author: Michal Meloun <[email protected]> AuthorDate: 2021-12-24 17:23:59 +0000 Commit: Michal Meloun <[email protected]> CommitDate: 2021-12-24 18:43:48 +0000 tegra210: Implement new get_gate method for tegra210 clocks. MFC after: 1 week --- sys/arm64/nvidia/tegra210/tegra210_clk_per.c | 20 ++++++++++++++++++++ sys/arm64/nvidia/tegra210/tegra210_clk_pll.c | 15 +++++++++++++++ 2 files changed, 35 insertions(+) diff --git a/sys/arm64/nvidia/tegra210/tegra210_clk_per.c b/sys/arm64/nvidia/tegra210/tegra210_clk_per.c index 302dd1d85fd3..edf842e1afac 100644 --- a/sys/arm64/nvidia/tegra210/tegra210_clk_per.c +++ b/sys/arm64/nvidia/tegra210/tegra210_clk_per.c @@ -811,6 +811,7 @@ periph_register(struct clkdom *clkdom, struct periph_def *clkdef) /* -------------------------------------------------------------------------- */ static int pgate_init(struct clknode *clk, device_t dev); static int pgate_set_gate(struct clknode *clk, bool enable); +static int pgate_get_gate(struct clknode *clk, bool *enabled); struct pgate_sc { device_t clkdev; @@ -824,6 +825,7 @@ static clknode_method_t pgate_methods[] = { /* Device interface */ CLKNODEMETHOD(clknode_init, pgate_init), CLKNODEMETHOD(clknode_set_gate, pgate_set_gate), + CLKNODEMETHOD(clknode_get_gate, pgate_get_gate), CLKNODEMETHOD_END }; DEFINE_CLASS_1(tegra210_pgate, tegra210_pgate_class, pgate_methods, @@ -885,6 +887,24 @@ pgate_set_gate(struct clknode *clk, bool enable) return(0); } +static int +pgate_get_gate(struct clknode *clk, bool *enabled) +{ + struct pgate_sc *sc; + uint32_t reg, mask, base_reg; + + sc = clknode_get_softc(clk); + mask = 1 << (sc->idx % 32); + base_reg = get_enable_reg(sc->idx); + + DEVICE_LOCK(sc); + RD4(sc, base_reg, ®); + DEVICE_UNLOCK(sc); + *enabled = reg & mask ? true: false; + + return(0); +} + int tegra210_hwreset_by_idx(struct tegra210_car_softc *sc, intptr_t idx, bool reset) { diff --git a/sys/arm64/nvidia/tegra210/tegra210_clk_pll.c b/sys/arm64/nvidia/tegra210/tegra210_clk_pll.c index 624404c3e074..64e3f6623d29 100644 --- a/sys/arm64/nvidia/tegra210/tegra210_clk_pll.c +++ b/sys/arm64/nvidia/tegra210/tegra210_clk_pll.c @@ -568,6 +568,7 @@ static struct clk_div_def tegra210_pll_divs[] = { static int tegra210_pll_init(struct clknode *clk, device_t dev); static int tegra210_pll_set_gate(struct clknode *clk, bool enable); +static int tegra210_pll_get_gate(struct clknode *clk, bool *enabled); static int tegra210_pll_recalc(struct clknode *clk, uint64_t *freq); static int tegra210_pll_set_freq(struct clknode *clknode, uint64_t fin, uint64_t *fout, int flags, int *stop); @@ -588,6 +589,7 @@ static clknode_method_t tegra210_pll_methods[] = { /* Device interface */ CLKNODEMETHOD(clknode_init, tegra210_pll_init), CLKNODEMETHOD(clknode_set_gate, tegra210_pll_set_gate), + CLKNODEMETHOD(clknode_get_gate, tegra210_pll_get_gate), CLKNODEMETHOD(clknode_recalc_freq, tegra210_pll_recalc), CLKNODEMETHOD(clknode_set_freq, tegra210_pll_set_freq), CLKNODEMETHOD_END @@ -886,6 +888,19 @@ tegra210_pll_set_gate(struct clknode *clknode, bool enable) return (rv); } +static int +tegra210_pll_get_gate(struct clknode *clknode, bool *enabled) +{ + uint32_t reg; + struct pll_sc *sc; + + sc = clknode_get_softc(clknode); + RD4(sc, sc->base_reg, ®); + *enabled = reg & PLL_BASE_ENABLE ? true: false; + WR4(sc, sc->base_reg, reg); + return (0); +} + static int pll_set_std(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags, uint32_t m, uint32_t n, uint32_t p)
