The branch main has been updated by kevans: URL: https://cgit.FreeBSD.org/src/commit/?id=93d4bad6453a2b32191428de69beb4766167db9d
commit 93d4bad6453a2b32191428de69beb4766167db9d Author: Kyle Evans <[email protected]> AuthorDate: 2023-10-27 03:55:17 +0000 Commit: Kyle Evans <[email protected]> CommitDate: 2023-10-27 03:55:17 +0000 arm: prune imx5 support from the tree The IMX5 configs were removed in advance of FreeBSD 14.0 in cdb0c2a73df ("arm: Remove IMX5 specific kernel configs"). This code isn't built with GENERIC and doesn't actually build today as-is, so let's remove it to avoid needless maintenance work to it that won't be tested. As usual, revival is welcome with a committed user and work to maintain it with upstream DTS and, ideally, in GENERIC. I note that vt_early_fb is now effectively orphaned as nothing else will use it, but I haven't yet removed it since I have not done anything to ascertain if it could be integrated easily enough for other SoC. It is among the files that doesn't actually build with today's clang, though. Reviewed by: imp, manu Differential Revision: https://reviews.freebsd.org/D41836 --- sys/arm/freescale/imx/files.imx5 | 54 -- sys/arm/freescale/imx/imx51_ccm.c | 656 ----------------------- sys/arm/freescale/imx/imx51_ccmreg.h | 257 --------- sys/arm/freescale/imx/imx51_ccmvar.h | 110 ---- sys/arm/freescale/imx/imx51_dpllreg.h | 105 ---- sys/arm/freescale/imx/imx51_ipuv3.c | 872 ------------------------------ sys/arm/freescale/imx/imx51_ipuv3_fbd.c | 360 ------------- sys/arm/freescale/imx/imx51_ipuv3reg.h | 922 -------------------------------- sys/arm/freescale/imx/imx51_machdep.c | 102 ---- sys/arm/freescale/imx/imx51_sdmareg.h | 141 ----- sys/arm/freescale/imx/imx51_ssireg.h | 179 ------- sys/arm/freescale/imx/imx51_tzicreg.h | 85 --- sys/arm/freescale/imx/imx53_machdep.c | 98 ---- sys/arm/freescale/imx/imx_nop_usbphy.c | 115 ---- sys/arm/freescale/imx/std.imx51 | 5 - sys/arm/freescale/imx/std.imx53 | 5 - sys/arm/freescale/imx/tzic.c | 306 ----------- sys/conf/options.arm | 2 - sys/dev/ata/chipsets/ata-fsl.c | 234 -------- 19 files changed, 4608 deletions(-) diff --git a/sys/arm/freescale/imx/files.imx5 b/sys/arm/freescale/imx/files.imx5 deleted file mode 100644 index 4522bf5021bd..000000000000 --- a/sys/arm/freescale/imx/files.imx5 +++ /dev/null @@ -1,54 +0,0 @@ - -# Init -arm/freescale/imx/imx_machdep.c standard -arm/freescale/imx/imx51_machdep.c optional soc_imx51 -arm/freescale/imx/imx53_machdep.c optional soc_imx53 - -# Special serial console for debuging early boot code -#arm/freescale/imx/imx_console.c standard - -# UART driver (includes serial console support) -dev/uart/uart_dev_imx.c optional uart - -# TrustZone Interrupt Controller -arm/freescale/imx/tzic.c standard - -# IOMUX - external pins multiplexor -arm/freescale/imx/imx_iomux.c standard - -# GPIO -arm/freescale/imx/imx_gpio.c optional gpio - -# Generic Periodic Timer -arm/freescale/imx/imx_gpt.c standard - -# Clock Configuration Manager -arm/freescale/imx/imx51_ccm.c standard - -# i.MX5xx PATA controller -dev/ata/chipsets/ata-fsl.c optional imxata - -# SDHCI/MMC -dev/sdhci/fsl_sdhci.c optional sdhci - -# USB OH3 controller (1 OTG, 3 EHCI) -arm/freescale/imx/imx_nop_usbphy.c optional ehci -dev/usb/controller/ehci_imx.c optional ehci - -# Watchdog -arm/freescale/imx/imx_wdog.c optional imxwdt - -# i2c -arm/freescale/imx/imx_i2c.c optional fsliic - -# IPU - Image Processing Unit (frame buffer also) -arm/freescale/imx/imx51_ipuv3.c optional sc -arm/freescale/imx/imx51_ipuv3_fbd.c optional vt -dev/vt/hw/fb/vt_early_fb.c optional vt - -# Fast Ethernet Controller -dev/ffec/if_ffec.c optional ffec - -# SPI -arm/freescale/imx/imx_spi.c optional imx_spi - diff --git a/sys/arm/freescale/imx/imx51_ccm.c b/sys/arm/freescale/imx/imx51_ccm.c deleted file mode 100644 index 3501a945b6ab..000000000000 --- a/sys/arm/freescale/imx/imx51_ccm.c +++ /dev/null @@ -1,656 +0,0 @@ -/* $NetBSD: imx51_ccm.c,v 1.1 2012/04/17 09:33:31 bsh Exp $ */ -/*- - * SPDX-License-Identifier: BSD-2-Clause - * - * Copyright (c) 2010, 2011, 2012 Genetec Corporation. All rights reserved. - * Written by Hashimoto Kenichi for Genetec Corporation. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -/*- - * Copyright (c) 2012, 2013 The FreeBSD Foundation - * All rights reserved. - * - * Portions of this software were developed by Oleksandr Rybalko - * under sponsorship from the FreeBSD Foundation. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -/* - * Clock Controller Module (CCM) - */ - -#include <sys/cdefs.h> -#include <sys/param.h> -#include <sys/systm.h> -#include <sys/bus.h> -#include <sys/kernel.h> -#include <sys/module.h> -#include <sys/malloc.h> -#include <sys/rman.h> -#include <machine/bus.h> -#include <machine/cpu.h> -#include <machine/intr.h> - -#include <dev/ofw/openfirm.h> -#include <dev/ofw/ofw_bus.h> -#include <dev/ofw/ofw_bus_subr.h> - -#include <machine/bus.h> -#include <machine/fdt.h> - -#include <arm/freescale/imx/imx51_ccmvar.h> -#include <arm/freescale/imx/imx51_ccmreg.h> -#include <arm/freescale/imx/imx51_dpllreg.h> -#include <arm/freescale/imx/imx_ccmvar.h> -#include <arm/freescale/imx/imx_machdep.h> - -#define IMXCCMDEBUG -#undef IMXCCMDEBUG - -#ifndef IMX51_OSC_FREQ -#define IMX51_OSC_FREQ (24 * 1000 * 1000) /* 24MHz */ -#endif - -#ifndef IMX51_CKIL_FREQ -#define IMX51_CKIL_FREQ 32768 -#endif - -/* - * The fdt data does not provide reg properties describing the DPLL register - * blocks we need to access, presumably because the needed addresses are - * hard-coded within the linux driver. That leaves us with no choice but to do - * the same thing, if we want to run with vendor-supplied fdt data. So here we - * have tables of the physical addresses we need for each soc, and we'll use - * bus_space_map() at attach() time to get access to them. - */ -static uint32_t imx51_dpll_addrs[IMX51_N_DPLLS] = { - 0x83f80000, /* DPLL1 */ - 0x83f84000, /* DPLL2 */ - 0x83f88000, /* DPLL3 */ -}; - -static uint32_t imx53_dpll_addrs[IMX51_N_DPLLS] = { - 0x63f80000, /* DPLL1 */ - 0x63f84000, /* DPLL2 */ - 0x63f88000, /* DPLL3 */ -}; - -#define DPLL_REGS_SZ (16 * 1024) - -struct imxccm_softc { - device_t sc_dev; - struct resource *ccmregs; - u_int64_t pll_freq[IMX51_N_DPLLS]; - bus_space_tag_t pllbst; - bus_space_handle_t pllbsh[IMX51_N_DPLLS]; -}; - -struct imxccm_softc *ccm_softc = NULL; - -static uint64_t imx51_get_pll_freq(u_int); - -static int imxccm_match(device_t); -static int imxccm_attach(device_t); - -static device_method_t imxccm_methods[] = { - DEVMETHOD(device_probe, imxccm_match), - DEVMETHOD(device_attach, imxccm_attach), - - DEVMETHOD_END -}; - -static driver_t imxccm_driver = { - "imxccm", - imxccm_methods, - sizeof(struct imxccm_softc), -}; - -EARLY_DRIVER_MODULE(imxccm, simplebus, imxccm_driver, 0, 0, BUS_PASS_CPU); - -static inline uint32_t -pll_read_4(struct imxccm_softc *sc, int pll, int reg) -{ - - return (bus_space_read_4(sc->pllbst, sc->pllbsh[pll - 1], reg)); -} - -static inline uint32_t -ccm_read_4(struct imxccm_softc *sc, int reg) -{ - - return (bus_read_4(sc->ccmregs, reg)); -} - -static inline void -ccm_write_4(struct imxccm_softc *sc, int reg, uint32_t val) -{ - - bus_write_4(sc->ccmregs, reg, val); -} - -static int -imxccm_match(device_t dev) -{ - - if (!ofw_bus_status_okay(dev)) - return (ENXIO); - - if (!ofw_bus_is_compatible(dev, "fsl,imx51-ccm") && - !ofw_bus_is_compatible(dev, "fsl,imx53-ccm")) - return (ENXIO); - - device_set_desc(dev, "Freescale Clock Control Module"); - return (BUS_PROBE_DEFAULT); -} - -static int -imxccm_attach(device_t dev) -{ - struct imxccm_softc *sc; - int idx; - u_int soc; - uint32_t *pll_addrs; - - sc = device_get_softc(dev); - sc->sc_dev = dev; - - switch ((soc = imx_soc_type())) { - case IMXSOC_51: - pll_addrs = imx51_dpll_addrs; - break; - case IMXSOC_53: - pll_addrs = imx53_dpll_addrs; - break; - default: - device_printf(dev, "No support for SoC type 0x%08x\n", soc); - goto noclocks; - } - - idx = 0; - sc->ccmregs = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &idx, - RF_ACTIVE); - if (sc->ccmregs == NULL) { - device_printf(dev, "could not allocate resources\n"); - goto noclocks; - } - - sc->pllbst = fdtbus_bs_tag; - for (idx = 0; idx < IMX51_N_DPLLS; ++idx) { - if (bus_space_map(sc->pllbst, pll_addrs[idx], DPLL_REGS_SZ, 0, - &sc->pllbsh[idx]) != 0) { - device_printf(dev, "Cannot map DPLL registers\n"); - goto noclocks; - } - } - - ccm_softc = sc; - - imx51_get_pll_freq(1); - imx51_get_pll_freq(2); - imx51_get_pll_freq(3); - - device_printf(dev, "PLL1=%lluMHz, PLL2=%lluMHz, PLL3=%lluMHz\n", - sc->pll_freq[0] / 1000000, - sc->pll_freq[1] / 1000000, - sc->pll_freq[2] / 1000000); - device_printf(dev, "CPU clock=%d, UART clock=%d\n", - imx51_get_clock(IMX51CLK_ARM_ROOT), - imx51_get_clock(IMX51CLK_UART_CLK_ROOT)); - device_printf(dev, - "mainbus clock=%d, ahb clock=%d ipg clock=%d perclk=%d\n", - imx51_get_clock(IMX51CLK_MAIN_BUS_CLK), - imx51_get_clock(IMX51CLK_AHB_CLK_ROOT), - imx51_get_clock(IMX51CLK_IPG_CLK_ROOT), - imx51_get_clock(IMX51CLK_PERCLK_ROOT)); - - return (0); - -noclocks: - - panic("Cannot continue without clock support"); -} - -u_int -imx51_get_clock(enum imx51_clock clk) -{ - u_int freq; - u_int sel; - uint32_t cacrr; /* ARM clock root register */ - uint32_t ccsr; - uint32_t cscdr1; - uint32_t cscmr1; - uint32_t cbcdr; - uint32_t cbcmr; - uint32_t cdcr; - - if (ccm_softc == NULL) - return (0); - - switch (clk) { - case IMX51CLK_PLL1: - case IMX51CLK_PLL2: - case IMX51CLK_PLL3: - return ccm_softc->pll_freq[clk-IMX51CLK_PLL1]; - case IMX51CLK_PLL1SW: - ccsr = ccm_read_4(ccm_softc, CCMC_CCSR); - if ((ccsr & CCSR_PLL1_SW_CLK_SEL) == 0) - return ccm_softc->pll_freq[1-1]; - /* step clock */ - /* FALLTHROUGH */ - case IMX51CLK_PLL1STEP: - ccsr = ccm_read_4(ccm_softc, CCMC_CCSR); - switch ((ccsr & CCSR_STEP_SEL_MASK) >> CCSR_STEP_SEL_SHIFT) { - case 0: - return imx51_get_clock(IMX51CLK_LP_APM); - case 1: - return 0; /* XXX PLL bypass clock */ - case 2: - return ccm_softc->pll_freq[2-1] / - (1 + ((ccsr & CCSR_PLL2_DIV_PODF_MASK) >> - CCSR_PLL2_DIV_PODF_SHIFT)); - case 3: - return ccm_softc->pll_freq[3-1] / - (1 + ((ccsr & CCSR_PLL3_DIV_PODF_MASK) >> - CCSR_PLL3_DIV_PODF_SHIFT)); - } - /*NOTREACHED*/ - case IMX51CLK_PLL2SW: - ccsr = ccm_read_4(ccm_softc, CCMC_CCSR); - if ((ccsr & CCSR_PLL2_SW_CLK_SEL) == 0) - return imx51_get_clock(IMX51CLK_PLL2); - return 0; /* XXX PLL2 bypass clk */ - case IMX51CLK_PLL3SW: - ccsr = ccm_read_4(ccm_softc, CCMC_CCSR); - if ((ccsr & CCSR_PLL3_SW_CLK_SEL) == 0) - return imx51_get_clock(IMX51CLK_PLL3); - return 0; /* XXX PLL3 bypass clk */ - - case IMX51CLK_LP_APM: - ccsr = ccm_read_4(ccm_softc, CCMC_CCSR); - return (ccsr & CCSR_LP_APM) ? - imx51_get_clock(IMX51CLK_FPM) : IMX51_OSC_FREQ; - - case IMX51CLK_ARM_ROOT: - freq = imx51_get_clock(IMX51CLK_PLL1SW); - cacrr = ccm_read_4(ccm_softc, CCMC_CACRR); - return freq / (cacrr + 1); - - /* ... */ - case IMX51CLK_MAIN_BUS_CLK_SRC: - cbcdr = ccm_read_4(ccm_softc, CCMC_CBCDR); - if ((cbcdr & CBCDR_PERIPH_CLK_SEL) == 0) - freq = imx51_get_clock(IMX51CLK_PLL2SW); - else { - freq = 0; - cbcmr = ccm_read_4(ccm_softc, CCMC_CBCMR); - switch ((cbcmr & CBCMR_PERIPH_APM_SEL_MASK) >> - CBCMR_PERIPH_APM_SEL_SHIFT) { - case 0: - freq = imx51_get_clock(IMX51CLK_PLL1SW); - break; - case 1: - freq = imx51_get_clock(IMX51CLK_PLL3SW); - break; - case 2: - freq = imx51_get_clock(IMX51CLK_LP_APM); - break; - case 3: - /* XXX: error */ - break; - } - } - return freq; - case IMX51CLK_MAIN_BUS_CLK: - freq = imx51_get_clock(IMX51CLK_MAIN_BUS_CLK_SRC); - cdcr = ccm_read_4(ccm_softc, CCMC_CDCR); - return freq / (1 + ((cdcr & CDCR_PERIPH_CLK_DVFS_PODF_MASK) >> - CDCR_PERIPH_CLK_DVFS_PODF_SHIFT)); - case IMX51CLK_AHB_CLK_ROOT: - freq = imx51_get_clock(IMX51CLK_MAIN_BUS_CLK); - cbcdr = ccm_read_4(ccm_softc, CCMC_CBCDR); - return freq / (1 + ((cbcdr & CBCDR_AHB_PODF_MASK) >> - CBCDR_AHB_PODF_SHIFT)); - case IMX51CLK_IPG_CLK_ROOT: - freq = imx51_get_clock(IMX51CLK_AHB_CLK_ROOT); - cbcdr = ccm_read_4(ccm_softc, CCMC_CBCDR); - return freq / (1 + ((cbcdr & CBCDR_IPG_PODF_MASK) >> - CBCDR_IPG_PODF_SHIFT)); - - case IMX51CLK_PERCLK_ROOT: - cbcmr = ccm_read_4(ccm_softc, CCMC_CBCMR); - if (cbcmr & CBCMR_PERCLK_IPG_SEL) - return imx51_get_clock(IMX51CLK_IPG_CLK_ROOT); - if (cbcmr & CBCMR_PERCLK_LP_APM_SEL) - freq = imx51_get_clock(IMX51CLK_LP_APM); - else - freq = imx51_get_clock(IMX51CLK_MAIN_BUS_CLK_SRC); - cbcdr = ccm_read_4(ccm_softc, CCMC_CBCDR); - -#ifdef IMXCCMDEBUG - printf("cbcmr=%x cbcdr=%x\n", cbcmr, cbcdr); -#endif - - freq /= 1 + ((cbcdr & CBCDR_PERCLK_PRED1_MASK) >> - CBCDR_PERCLK_PRED1_SHIFT); - freq /= 1 + ((cbcdr & CBCDR_PERCLK_PRED2_MASK) >> - CBCDR_PERCLK_PRED2_SHIFT); - freq /= 1 + ((cbcdr & CBCDR_PERCLK_PODF_MASK) >> - CBCDR_PERCLK_PODF_SHIFT); - return freq; - case IMX51CLK_UART_CLK_ROOT: - cscdr1 = ccm_read_4(ccm_softc, CCMC_CSCDR1); - cscmr1 = ccm_read_4(ccm_softc, CCMC_CSCMR1); - -#ifdef IMXCCMDEBUG - printf("cscdr1=%x cscmr1=%x\n", cscdr1, cscmr1); -#endif - - sel = (cscmr1 & CSCMR1_UART_CLK_SEL_MASK) >> - CSCMR1_UART_CLK_SEL_SHIFT; - - freq = 0; /* shut up GCC */ - switch (sel) { - case 0: - case 1: - case 2: - freq = imx51_get_clock(IMX51CLK_PLL1SW + sel); - break; - case 3: - freq = imx51_get_clock(IMX51CLK_LP_APM); - break; - } - - return freq / (1 + ((cscdr1 & CSCDR1_UART_CLK_PRED_MASK) >> - CSCDR1_UART_CLK_PRED_SHIFT)) / - (1 + ((cscdr1 & CSCDR1_UART_CLK_PODF_MASK) >> - CSCDR1_UART_CLK_PODF_SHIFT)); - case IMX51CLK_IPU_HSP_CLK_ROOT: - freq = 0; - cbcmr = ccm_read_4(ccm_softc, CCMC_CBCMR); - switch ((cbcmr & CBCMR_IPU_HSP_CLK_SEL_MASK) >> - CBCMR_IPU_HSP_CLK_SEL_SHIFT) { - case 0: - freq = imx51_get_clock(IMX51CLK_ARM_AXI_A_CLK); - break; - case 1: - freq = imx51_get_clock(IMX51CLK_ARM_AXI_B_CLK); - break; - case 2: - freq = imx51_get_clock( - IMX51CLK_EMI_SLOW_CLK_ROOT); - break; - case 3: - freq = imx51_get_clock(IMX51CLK_AHB_CLK_ROOT); - break; - } - return freq; - default: - device_printf(ccm_softc->sc_dev, - "clock %d: not supported yet\n", clk); - return 0; - } -} - -static uint64_t -imx51_get_pll_freq(u_int pll_no) -{ - uint32_t dp_ctrl; - uint32_t dp_op; - uint32_t dp_mfd; - uint32_t dp_mfn; - uint32_t mfi; - int32_t mfn; - uint32_t mfd; - uint32_t pdf; - uint32_t ccr; - uint64_t freq = 0; - u_int ref = 0; - - KASSERT(1 <= pll_no && pll_no <= IMX51_N_DPLLS, ("Wrong PLL id")); - - dp_ctrl = pll_read_4(ccm_softc, pll_no, DPLL_DP_CTL); - - if (dp_ctrl & DP_CTL_HFSM) { - dp_op = pll_read_4(ccm_softc, pll_no, DPLL_DP_HFS_OP); - dp_mfd = pll_read_4(ccm_softc, pll_no, DPLL_DP_HFS_MFD); - dp_mfn = pll_read_4(ccm_softc, pll_no, DPLL_DP_HFS_MFN); - } else { - dp_op = pll_read_4(ccm_softc, pll_no, DPLL_DP_OP); - dp_mfd = pll_read_4(ccm_softc, pll_no, DPLL_DP_MFD); - dp_mfn = pll_read_4(ccm_softc, pll_no, DPLL_DP_MFN); - } - - pdf = dp_op & DP_OP_PDF_MASK; - mfi = max(5, (dp_op & DP_OP_MFI_MASK) >> DP_OP_MFI_SHIFT); - mfd = dp_mfd; - if (dp_mfn & 0x04000000) - /* 27bit signed value */ - mfn = (uint32_t)(0xf8000000 | dp_mfn); - else - mfn = dp_mfn; - - switch (dp_ctrl & DP_CTL_REF_CLK_SEL_MASK) { - case DP_CTL_REF_CLK_SEL_COSC: - /* Internal Oscillator */ - /* TODO: get from FDT "fsl,imx-osc" */ - ref = 24000000; /* IMX51_OSC_FREQ */ - break; - case DP_CTL_REF_CLK_SEL_FPM: - ccr = ccm_read_4(ccm_softc, CCMC_CCR); - if (ccr & CCR_FPM_MULT) - /* TODO: get from FDT "fsl,imx-ckil" */ - ref = 32768 * 1024; - else - /* TODO: get from FDT "fsl,imx-ckil" */ - ref = 32768 * 512; - break; - default: - ref = 0; - } - - if (dp_ctrl & DP_CTL_REF_CLK_DIV) - ref /= 2; - - ref *= 4; - freq = (int64_t)ref * mfi + (int64_t)ref * mfn / (mfd + 1); - freq /= pdf + 1; - - if (!(dp_ctrl & DP_CTL_DPDCK0_2_EN)) - freq /= 2; - -#ifdef IMXCCMDEBUG - printf("ref: %dKHz ", ref); - printf("dp_ctl: %08x ", dp_ctrl); - printf("pdf: %3d ", pdf); - printf("mfi: %3d ", mfi); - printf("mfd: %3d ", mfd); - printf("mfn: %3d ", mfn); - printf("pll: %d\n", (uint32_t)freq); -#endif - - ccm_softc->pll_freq[pll_no-1] = freq; - - return (freq); -} - -void -imx51_clk_gating(int clk_src, int mode) -{ - int field, group; - uint32_t reg; - - group = CCMR_CCGR_MODULE(clk_src); - field = clk_src % CCMR_CCGR_NSOURCE; - reg = ccm_read_4(ccm_softc, CCMC_CCGR(group)); - reg &= ~(0x03 << field * 2); - reg |= (mode << field * 2); - ccm_write_4(ccm_softc, CCMC_CCGR(group), reg); -} - -int -imx51_get_clk_gating(int clk_src) -{ - uint32_t reg; - - reg = ccm_read_4(ccm_softc, - CCMC_CCGR(CCMR_CCGR_MODULE(clk_src))); - return ((reg >> (clk_src % CCMR_CCGR_NSOURCE) * 2) & 0x03); -} - -/* - * Code from here down is temporary, in lieu of a SoC-independent clock API. - */ - -void -imx_ccm_usb_enable(device_t dev) -{ - uint32_t regval; - - /* - * Select PLL2 as the source for the USB clock. - * The default is PLL3, but U-boot changes it to PLL2. - */ - regval = ccm_read_4(ccm_softc, CCMC_CSCMR1); - regval &= ~CSCMR1_USBOH3_CLK_SEL_MASK; - regval |= 1 << CSCMR1_USBOH3_CLK_SEL_SHIFT; - ccm_write_4(ccm_softc, CCMC_CSCMR1, regval); - - /* - * Set the USB clock pre-divider to div-by-5, post-divider to div-by-2. - */ - regval = ccm_read_4(ccm_softc, CCMC_CSCDR1); - regval &= ~CSCDR1_USBOH3_CLK_PODF_MASK; - regval &= ~CSCDR1_USBOH3_CLK_PRED_MASK; - regval |= 4 << CSCDR1_USBOH3_CLK_PRED_SHIFT; - regval |= 1 << CSCDR1_USBOH3_CLK_PODF_SHIFT; - ccm_write_4(ccm_softc, CCMC_CSCDR1, regval); - - /* - * The same two clocks gates are used on imx51 and imx53. - */ - imx51_clk_gating(CCGR_USBOH3_IPG_AHB_CLK, CCGR_CLK_MODE_ALWAYS); - imx51_clk_gating(CCGR_USBOH3_60M_CLK, CCGR_CLK_MODE_ALWAYS); -} - -void -imx_ccm_usbphy_enable(device_t dev) -{ - uint32_t regval; - - /* - * Select PLL3 as the source for the USBPHY clock. U-boot does this - * only for imx53, but the bit exists on imx51. That seems a bit - * strange, but we'll go with it until more is known. - */ - if (imx_soc_type() == IMXSOC_53) { - regval = ccm_read_4(ccm_softc, CCMC_CSCMR1); - regval |= 1 << CSCMR1_USBPHY_CLK_SEL_SHIFT; - ccm_write_4(ccm_softc, CCMC_CSCMR1, regval); - } - - /* - * For the imx51 there's just one phy gate control, enable it. - */ - if (imx_soc_type() == IMXSOC_51) { - imx51_clk_gating(CCGR_USB_PHY_CLK, CCGR_CLK_MODE_ALWAYS); - return; - } - - /* - * For imx53 we don't have a full set of clock defines yet, but the - * datasheet says: - * gate reg 4, bits 13-12 usb ph2 clock (usb_phy2_clk_enable) - * gate reg 4, bits 11-10 usb ph1 clock (usb_phy1_clk_enable) - * - * We should use the fdt data for the device to figure out which of - * the two we're working on, but for now just turn them both on. - */ - if (imx_soc_type() == IMXSOC_53) { - imx51_clk_gating(__CCGR_NUM(4, 5), CCGR_CLK_MODE_ALWAYS); - imx51_clk_gating(__CCGR_NUM(4, 6), CCGR_CLK_MODE_ALWAYS); - return; - } -} - -uint32_t -imx_ccm_ecspi_hz(void) -{ - - return (imx51_get_clock(IMX51CLK_CSPI_CLK_ROOT)); -} - -uint32_t -imx_ccm_ipg_hz(void) -{ - - return (imx51_get_clock(IMX51CLK_IPG_CLK_ROOT)); -} - -uint32_t -imx_ccm_sdhci_hz(void) -{ - - return (imx51_get_clock(IMX51CLK_ESDHC1_CLK_ROOT)); -} - -uint32_t -imx_ccm_perclk_hz(void) -{ - - return (imx51_get_clock(IMX51CLK_PERCLK_ROOT)); -} - -uint32_t -imx_ccm_uart_hz(void) -{ - - return (imx51_get_clock(IMX51CLK_UART_CLK_ROOT)); -} - -uint32_t -imx_ccm_ahb_hz(void) -{ - - return (imx51_get_clock(IMX51CLK_AHB_CLK_ROOT)); -} diff --git a/sys/arm/freescale/imx/imx51_ccmreg.h b/sys/arm/freescale/imx/imx51_ccmreg.h deleted file mode 100644 index 5fa56af0227b..000000000000 --- a/sys/arm/freescale/imx/imx51_ccmreg.h +++ /dev/null @@ -1,257 +0,0 @@ -/* $NetBSD: imx51_ccmreg.h,v 1.1 2012/04/17 09:33:31 bsh Exp $ */ -/*- - * SPDX-License-Identifier: BSD-2-Clause - * - * Copyright (c) 2011, 2012 Genetec Corporation. All rights reserved. - * Written by Hashimoto Kenichi for Genetec Corporation. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -/*- - * Copyright (c) 2012, 2013 The FreeBSD Foundation - * All rights reserved. - * - * Portions of this software were developed by Oleksandr Rybalko - * under sponsorship from the FreeBSD Foundation. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#ifndef _IMX51_CCMREG_H -#define _IMX51_CCMREG_H - -#include <sys/cdefs.h> - -/* register offset address */ - -#define CCMC_BASE 0x73fd4000 -#define CCMC_CCR 0x0000 -#define CCR_FPM_MULT 0x00001000 -#define CCMC_CCDR 0x0004 -#define CCMC_CSR 0x0008 -#define CCMC_CCSR 0x000c -#define CCSR_LP_APM 0x00000200 -#define CCSR_STEP_SEL_SHIFT 7 -#define CCSR_STEP_SEL_MASK 0x00000180 -#define CCSR_PLL2_DIV_PODF_SHIFT 5 -#define CCSR_PLL2_DIV_PODF_MASK 0x00000060 -#define CCSR_PLL3_DIV_PODF_SHIFT 3 -#define CCSR_PLL3_DIV_PODF_MASK 0x00000030 -#define CCSR_PLL1_SW_CLK_SEL 0x00000004 -#define CCSR_PLL2_SW_CLK_SEL 0x00000002 -#define CCSR_PLL3_SW_CLK_SEL 0x00000001 -#define CCMC_CACRR 0x0010 -#define CCMC_CBCDR 0x0014 -#define CBCDR_DDR_HIGH_FREQ_CLK_SEL 0x40000000 -#define CBCDR_DDR_CLK_PODF_SHIFT 27 -#define CBCDR_DDR_CLK_PODF_MASK 0x38000000 -#define CBCDR_EMI_CLK_SEL 0x04000000 -#define CBCDR_PERIPH_CLK_SEL 0x02000000 -#define CBCDR_EMI_SLOW_PODF_SHIFT 22 -#define CBCDR_EMI_SLOW_PODF_MASK 0x01c00000 -#define CBCDR_AXI_B_PODF_SHIFT 19 -#define CBCDR_AXI_B_PODF_MASK 0x00380000 -#define CBCDR_AXI_A_PODF_SHIFT 16 -#define CBCDR_AXI_A_PODF_MASK 0x1fff0000 -#define CBCDR_NFC_PODF_SHIFT 13 -#define CBCDR_NFC_PODF_MASK 0x00018000 -#define CBCDR_AHB_PODF_SHIFT 10 -#define CBCDR_AHB_PODF_MASK 0x00001c00 -#define CBCDR_IPG_PODF_SHIFT 8 -#define CBCDR_IPG_PODF_MASK 0x00000300 -#define CBCDR_PERCLK_PRED1_SHIFT 6 -#define CBCDR_PERCLK_PRED1_MASK 0x000000c0 -#define CBCDR_PERCLK_PRED2_SHIFT 3 -#define CBCDR_PERCLK_PRED2_MASK 0x00000038 -#define CBCDR_PERCLK_PODF_SHIFT 0 -#define CBCDR_PERCLK_PODF_MASK 0x00000007 -#define CCMC_CBCMR 0x0018 -#define CBCMR_PERIPH_APM_SEL_SHIFT 12 -#define CBCMR_PERIPH_APM_SEL_MASK 0x00003000 -#define CBCMR_IPU_HSP_CLK_SEL_SHIFT 6 -#define CBCMR_IPU_HSP_CLK_SEL_MASK 0x000000c0 -#define CBCMR_PERCLK_LP_APM_SEL 0x00000002 -#define CBCMR_PERCLK_IPG_SEL 0x00000001 -#define CCMC_CSCMR1 0x001c -#define CSCMR1_UART_CLK_SEL_SHIFT 24 -#define CSCMR1_UART_CLK_SEL_MASK 0x03000000 -#define CSCMR1_USBPHY_CLK_SEL_SHIFT 26 -#define CSCMR1_USBPHY_CLK_SEL_MASK 0x04000000 -#define CSCMR1_USBOH3_CLK_SEL_SHIFT 22 -#define CSCMR1_USBOH3_CLK_SEL_MASK 0x00c00000 -#define CCMC_CSCMR2 0x0020 -#define CCMC_CSCDR1 0x0024 -#define CSCDR1_UART_CLK_PRED_SHIFT 3 -#define CSCDR1_UART_CLK_PRED_MASK 0x00000038 -#define CSCDR1_UART_CLK_PODF_SHIFT 0 -#define CSCDR1_UART_CLK_PODF_MASK 0x00000007 -#define CSCDR1_USBOH3_CLK_PRED_SHIFT 8 -#define CSCDR1_USBOH3_CLK_PRED_MASK 0x00000700 -#define CSCDR1_USBOH3_CLK_PODF_SHIFT 6 -#define CSCDR1_USBOH3_CLK_PODF_MASK 0x000000c0 -#define CCMC_CS1CDR 0x0028 -#define CCMC_CS2CDR 0x002c -#define CCMC_CDCDR 0x0030 -#define CCMC_CSCDR2 0x0038 -#define CCMC_CSCDR3 0x003c -#define CCMC_CSCDR4 0x0040 -#define CCMC_CWDR 0x0044 -#define CCMC_CDHIPR 0x0048 -#define CCMC_CDCR 0x004c -#define CDCR_PERIPH_CLK_DVFS_PODF_SHIFT 0 -#define CDCR_PERIPH_CLK_DVFS_PODF_MASK 0x00000003 -#define CCMC_CTOR 0x0050 -#define CCMC_CLPCR 0x0054 -#define CCMC_CISR 0x0058 -#define CCMC_CIMR 0x005c -#define CCMC_CCOSR 0x0060 -#define CCMC_CGPR 0x0064 -#define CCMC_CCGR(n) (0x0068 + (n) * 4) -#define CCMC_CMEOR 0x0084 - -#define CCMC_SIZE 0x88 - -/* CCGR Clock Gate Register */ - -#define CCMR_CCGR_NSOURCE 16 -#define CCMR_CCGR_NGROUPS 7 -#define CCMR_CCGR_MODULE(clk) ((clk) / CCMR_CCGR_NSOURCE) -#define __CCGR_NUM(a, b) ((a) * 16 + (b)) - -#define CCGR_ARM_BUS_CLK __CCGR_NUM(0, 0) -#define CCGR_ARM_AXI_CLK __CCGR_NUM(0, 1) -#define CCGR_ARM_DEBUG_CLK __CCGR_NUM(0, 2) -#define CCGR_TZIC_CLK __CCGR_NUM(0, 3) -#define CCGR_DAP_CLK __CCGR_NUM(0, 4) -#define CCGR_TPIU_CLK __CCGR_NUM(0, 5) -#define CCGR_CTI2_CLK __CCGR_NUM(0, 6) -#define CCGR_CTI3_CLK __CCGR_NUM(0, 7) -#define CCGR_AHBMUX1_CLK __CCGR_NUM(0, 8) -#define CCGR_AHBMUX2_CLK __CCGR_NUM(0, 9) -#define CCGR_ROMCP_CLK __CCGR_NUM(0, 10) -#define CCGR_ROM_CLK __CCGR_NUM(0, 11) -#define CCGR_AIPS_TZ1_CLK __CCGR_NUM(0, 12) -#define CCGR_AIPS_TZ2_CLK __CCGR_NUM(0, 13) -#define CCGR_AHB_MAX_CLK __CCGR_NUM(0, 14) -#define CCGR_IIM_CLK __CCGR_NUM(0, 15) -#define CCGR_TMAX1_CLK __CCGR_NUM(1, 0) -#define CCGR_TMAX2_CLK __CCGR_NUM(1, 1) -#define CCGR_TMAX3_CLK __CCGR_NUM(1, 2) -#define CCGR_UART1_CLK __CCGR_NUM(1, 3) -#define CCGR_UART1_SERIAL_CLK __CCGR_NUM(1, 4) -#define CCGR_UART2_CLK __CCGR_NUM(1, 5) -#define CCGR_UART2_SERIAL_CLK __CCGR_NUM(1, 6) -#define CCGR_UART3_CLK __CCGR_NUM(1, 7) -#define CCGR_UART3_SERIAL_CLK __CCGR_NUM(1, 8) -#define CCGR_I2C1_SERIAL_CLK __CCGR_NUM(1, 9) -#define CCGR_I2C2_SERIAL_CLK __CCGR_NUM(1, 10) -#define CCGR_HSI2C_CLK __CCGR_NUM(1, 11) -#define CCGR_HSI2C_SERIAL_CLK __CCGR_NUM(1, 12) -#define CCGR_FIRI_CLK __CCGR_NUM(1, 13) -#define CCGR_FIRI_SERIAL_CLK __CCGR_NUM(1, 14) -#define CCGR_SCC_CLK __CCGR_NUM(1, 15) - -#define CCGR_USB_PHY_CLK __CCGR_NUM(2, 0) -#define CCGR_EPIT1_CLK __CCGR_NUM(2, 1) -#define CCGR_EPIT1_SERIAL_CLK __CCGR_NUM(2, 2) -#define CCGR_EPIT2_CLK __CCGR_NUM(2, 3) -#define CCGR_EPIT2_SERIAL_CLK __CCGR_NUM(2, 4) -#define CCGR_PWM1_CLK __CCGR_NUM(2, 5) -#define CCGR_PWM1_SERIAL_CLK __CCGR_NUM(2, 6) -#define CCGR_PWM2_CLK __CCGR_NUM(2, 7) -#define CCGR_PWM2_SERIAL_CLK __CCGR_NUM(2, 8) -#define CCGR_GPT_CLK __CCGR_NUM(2, 9) -#define CCGR_GPT_SERIAL_CLK __CCGR_NUM(2, 10) -#define CCGR_OWIRE_CLK __CCGR_NUM(2, 11) -#define CCGR_FEC_CLK __CCGR_NUM(2, 12) -#define CCGR_USBOH3_IPG_AHB_CLK __CCGR_NUM(2, 13) -#define CCGR_USBOH3_60M_CLK __CCGR_NUM(2, 14) -#define CCGR_TVE_CLK __CCGR_NUM(2, 15) - -#define CCGR_ESDHC1_CLK __CCGR_NUM(3, 0) *** 3789 LINES SKIPPED ***
