The branch main has been updated by andrew: URL: https://cgit.FreeBSD.org/src/commit/?id=57ef7935eb114e98e7e554c5ffbded68fd038c04
commit 57ef7935eb114e98e7e554c5ffbded68fd038c04 Author: Andrew Turner <[email protected]> AuthorDate: 2024-07-23 09:18:08 +0000 Commit: Andrew Turner <[email protected]> CommitDate: 2024-07-23 09:25:05 +0000 arm64: Fix the gicv3 check in locore.S In locore.S we need to configure access to the GICv3. To check if it's available we read the id_aa64pfr0_el1 register, however we then only check if a GICv3.0 or 4.0 is present. If the system has a GICv4.1 this check would fail. Move to checking if the GICV3+ is not absent so this will still work if the field is updated again. Sponsored by: Arm Ltd Differential Revision: https://reviews.freebsd.org/D45530 --- sys/arm64/arm64/locore.S | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/sys/arm64/arm64/locore.S b/sys/arm64/arm64/locore.S index 2680669c61f8..3dcb01fd2a6e 100644 --- a/sys/arm64/arm64/locore.S +++ b/sys/arm64/arm64/locore.S @@ -389,9 +389,8 @@ LENTRY(enter_kernel_el) mrs x2, id_aa64pfr0_el1 /* Extract GIC bits from the register */ ubfx x2, x2, #ID_AA64PFR0_GIC_SHIFT, #ID_AA64PFR0_GIC_BITS - /* GIC[3:0] == 0001 - GIC CPU interface via special regs. supported */ - cmp x2, #(ID_AA64PFR0_GIC_CPUIF_EN >> ID_AA64PFR0_GIC_SHIFT) - b.ne 2f + /* GIC[3:0] != 0000 - GIC CPU interface via special regs. supported */ + cbz x2, 2f mrs x2, icc_sre_el2 orr x2, x2, #ICC_SRE_EL2_EN /* Enable access from insecure EL1 */
