The branch main has been updated by andrew: URL: https://cgit.FreeBSD.org/src/commit/?id=3a3aa2cc07563e288950affbda6b743487e9d49d
commit 3a3aa2cc07563e288950affbda6b743487e9d49d Author: Andrew Turner <[email protected]> AuthorDate: 2024-09-05 12:11:48 +0000 Commit: Andrew Turner <[email protected]> CommitDate: 2024-09-05 12:12:16 +0000 arm64: Remove TCR_CACHE_ATTRS and TCR_SMP_ATTRS These are only used in one place so expand them there. While here always set TCR_SH0_IS and TCR_SH1_IS. There is no advantage to not set them in a UP kernel. Reviewed by: alc, kib, markj Sponsored by: Arm Ltd Differential Revision: https://reviews.freebsd.org/D46393 --- sys/arm64/arm64/locore.S | 5 +++-- sys/arm64/include/armreg.h | 8 -------- 2 files changed, 3 insertions(+), 10 deletions(-) diff --git a/sys/arm64/arm64/locore.S b/sys/arm64/arm64/locore.S index ae1a005fd68f..daf8a936eda2 100644 --- a/sys/arm64/arm64/locore.S +++ b/sys/arm64/arm64/locore.S @@ -945,8 +945,9 @@ tcr: #error Unsupported page size #endif - .quad (TCR_TxSZ(64 - VIRT_BITS) | TCR_TG | \ - TCR_CACHE_ATTRS | TCR_SMP_ATTRS) + .quad (TCR_TxSZ(64 - VIRT_BITS) | TCR_TG | \ + TCR_SH1_IS | TCR_ORGN1_WBWA | TCR_IRGN1_WBWA | \ + TCR_SH0_IS | TCR_ORGN0_WBWA | TCR_IRGN0_WBWA) sctlr_set: /* Bits to set */ .quad (SCTLR_LSMAOE | SCTLR_nTLSMD | SCTLR_UCI | SCTLR_SPAN | \ diff --git a/sys/arm64/include/armreg.h b/sys/arm64/include/armreg.h index b4adc3d2c254..54600d63891e 100644 --- a/sys/arm64/include/armreg.h +++ b/sys/arm64/include/armreg.h @@ -2543,14 +2543,6 @@ #define TCR_T0SZ(x) ((x) << TCR_T0SZ_SHIFT) #define TCR_TxSZ(x) (TCR_T1SZ(x) | TCR_T0SZ(x)) -#define TCR_CACHE_ATTRS ((TCR_IRGN0_WBWA | TCR_IRGN1_WBWA) |\ - (TCR_ORGN0_WBWA | TCR_ORGN1_WBWA)) -#ifdef SMP -#define TCR_SMP_ATTRS (TCR_SH0_IS | TCR_SH1_IS) -#else -#define TCR_SMP_ATTRS 0 -#endif - /* TCR_EL12 */ #define TCR_EL12_REG MRS_REG_ALT_NAME(TCR_EL12) #define TCR_EL12_op0 3
