The branch main has been updated by jhibbits:

URL: 
https://cgit.FreeBSD.org/src/commit/?id=fe73eb441f1c98fe350f4822c7d2abfeef046bf8

commit fe73eb441f1c98fe350f4822c7d2abfeef046bf8
Author:     Justin Hibbits <jhibb...@freebsd.org>
AuthorDate: 2025-03-19 22:25:40 +0000
Commit:     Justin Hibbits <jhibb...@freebsd.org>
CommitDate: 2025-03-19 22:35:17 +0000

    powernv: Explicitly enable the facilities we support
    
    Thus far we've relied on the firmware setting HFSCR correctly, enabling
    all facilities.  However, it appears some recent firmwares do not.
    Linux explicitly enables all facilities it supports (including
    transactional memory, which new firmwares apparently do not enable), so
    do the same here, explicitly enable all the facilities FreeBSD supports.
    
    MFC after:      1 week
---
 sys/powerpc/include/spr.h              | 5 +++++
 sys/powerpc/powernv/platform_powernv.c | 6 ++++++
 2 files changed, 11 insertions(+)

diff --git a/sys/powerpc/include/spr.h b/sys/powerpc/include/spr.h
index 5bb3858b0fb5..605b1be194d9 100644
--- a/sys/powerpc/include/spr.h
+++ b/sys/powerpc/include/spr.h
@@ -162,6 +162,11 @@
 #define          FSCR_DSCR               0x0000000000000004 /* DSCR available 
in PR state */
 #define        SPR_UAMOR               0x09d   /* User Authority Mask Override 
Register */
 #define        SPR_DPDES               0x0b0   /* .6. Directed Privileged 
Doorbell Exception State Register */
+#define        SPR_HFSCR               0xbe    /* Hypervisor Facility Status 
and Control Register */
+#define          HFSCR_BHRB              0x0000000000000010 /* BHRB 
instructions */
+#define          HFSCR_PM                0x0000000000000008 /* Performance 
monitor SPRs */
+#define          HFSCR_VECVSX            0x0000000000000002 /* Vector and VSX 
facilities */
+#define          HFSCR_FP                0x0000000000000001 /* Floating Point 
facility */
 #define        SPR_USPRG0              0x100   /* 4.8 User SPR General 0 */
 #define        SPR_VRSAVE              0x100   /* .6. AltiVec VRSAVE */
 #define        SPR_SPRG0               0x110   /* 468 SPR General 0 */
diff --git a/sys/powerpc/powernv/platform_powernv.c 
b/sys/powerpc/powernv/platform_powernv.c
index 50af24794e69..678631322173 100644
--- a/sys/powerpc/powernv/platform_powernv.c
+++ b/sys/powerpc/powernv/platform_powernv.c
@@ -138,6 +138,7 @@ powernv_attach(platform_t plat)
        phandle_t opal;
        int res, len, idx;
        register_t msr;
+       register_t fscr;
        bool has_lp;
 
        /* Ping OPAL again just to make sure */
@@ -179,6 +180,11 @@ powernv_attach(platform_t plat)
        mtspr(SPR_LPCR, lpcr);
        isync();
 
+       fscr = mfspr(SPR_HFSCR);
+       fscr |= FSCR_TAR | FSCR_EBB | HFSCR_BHRB | HFSCR_PM |
+           HFSCR_VECVSX | HFSCR_FP | FSCR_MSGP | FSCR_DSCR;
+       mtspr(SPR_HFSCR, fscr);
+
        mtmsr(msr);
 
        powernv_cpuref_init();

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