The branch main has been updated by br:
URL:
https://cgit.FreeBSD.org/src/commit/?id=6d58c670060a17817fa0c8ebf4e7543c3d2b4523
commit 6d58c670060a17817fa0c8ebf4e7543c3d2b4523
Author: Ruslan Bukin <b...@freebsd.org>
AuthorDate: 2025-03-26 08:09:50 +0000
Commit: Ruslan Bukin <b...@freebsd.org>
CommitDate: 2025-03-26 08:22:50 +0000
riscv timer: fix interrupt handling.
Based on the spec the STIP bit of SIP register is read-only.
To clear STIP bit from supervisor we have to do an SBI call to firmware.
Upon reception of SBI request, the machine-mode firmware clears the STIP
bit in the MIP register.
This fixes operation on Codasip A730.
Reviewed by: mhorne
Differential Revision: https://reviews.freebsd.org/D49487
---
sys/riscv/riscv/timer.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/sys/riscv/riscv/timer.c b/sys/riscv/riscv/timer.c
index dc909082edae..652e5c8db62b 100644
--- a/sys/riscv/riscv/timer.c
+++ b/sys/riscv/riscv/timer.c
@@ -1,5 +1,5 @@
/*-
- * Copyright (c) 2015-2024 Ruslan Bukin <b...@bsdpad.com>
+ * Copyright (c) 2015-2025 Ruslan Bukin <b...@bsdpad.com>
* All rights reserved.
*
* Portions of this software were developed by SRI International and the
@@ -146,7 +146,7 @@ riscv_timer_intr(void *arg)
if (has_sstc)
csr_write(stimecmp, -1UL);
else
- csr_clear(sip, SIP_STIP);
+ sbi_set_timer(-1UL);
if (sc->et.et_active)
sc->et.et_event_cb(&sc->et, sc->et.et_arg);
