The branch main has been updated by np: URL: https://cgit.FreeBSD.org/src/commit/?id=bc48ca42d0d40b0b88df9cc1d8aec49533529690
commit bc48ca42d0d40b0b88df9cc1d8aec49533529690 Author: Navdeep Parhar <[email protected]> AuthorDate: 2025-09-29 13:22:47 +0000 Commit: Navdeep Parhar <[email protected]> CommitDate: 2025-09-29 14:26:01 +0000 cxgbetool(8): Updates for T7 * Registers dump * SGE context * TCB info MFC after: 3 days Sponsored by: Chelsio Communications --- usr.sbin/cxgbetool/Makefile | 1 + usr.sbin/cxgbetool/cxgbetool.c | 257 +- usr.sbin/cxgbetool/reg_defs_t4vf.c | 15 + usr.sbin/cxgbetool/reg_defs_t7.c | 28216 +++++++++++++++++++++++++++++++++++ usr.sbin/cxgbetool/tcb_common.c | 22 +- usr.sbin/cxgbetool/tcbinfot7.c | 1512 ++ usr.sbin/cxgbetool/tcbshowt7.c | 412 + 7 files changed, 30426 insertions(+), 9 deletions(-) diff --git a/usr.sbin/cxgbetool/Makefile b/usr.sbin/cxgbetool/Makefile index cc5290b8aaf5..bf24b11c18c8 100644 --- a/usr.sbin/cxgbetool/Makefile +++ b/usr.sbin/cxgbetool/Makefile @@ -6,6 +6,7 @@ SRCS+= tcb_common.c SRCS+= tcbinfot4.c tcbshowt4.c SRCS+= tcbinfot5.c tcbshowt5.c SRCS+= tcbinfot6.c tcbshowt6.c +SRCS+= tcbinfot7.c tcbshowt7.c CFLAGS+= -I${SRCTOP}/sys/dev/cxgbe -I${SRCTOP}/sys -I. LIBADD= pcap WARNS?= 2 diff --git a/usr.sbin/cxgbetool/cxgbetool.c b/usr.sbin/cxgbetool/cxgbetool.c index c3bd883b39fc..68de86d74092 100644 --- a/usr.sbin/cxgbetool/cxgbetool.c +++ b/usr.sbin/cxgbetool/cxgbetool.c @@ -1,6 +1,5 @@ /*- - * Copyright (c) 2011 Chelsio Communications, Inc. - * All rights reserved. + * Copyright (c) 2011, 2025 Chelsio Communications. * Written by: Navdeep Parhar <[email protected]> * * Redistribution and use in source and binary forms, with or without @@ -92,6 +91,7 @@ struct field_desc { #include "reg_defs_t4.c" #include "reg_defs_t5.c" #include "reg_defs_t6.c" +#include "reg_defs_t7.c" #include "reg_defs_t4vf.c" static void @@ -436,6 +436,48 @@ dump_regs_t6(int argc, const char *argv[], const uint32_t *regs) } #undef T6_MODREGS +#define T7_MODREGS(name) { #name, t7_##name##_regs } +static int +dump_regs_t7(int argc, const char *argv[], const uint32_t *regs) +{ + static struct mod_regs t7_mod[] = { + T7_MODREGS(sge), + { "pci", t7_pcie_regs }, + T7_MODREGS(dbg), + { "mc0", t7_mc_t70_regs }, + T7_MODREGS(ma), + { "edc0", t7_edc_t60_regs }, + { "edc1", t7_edc_t61_regs }, + T7_MODREGS(cim), + T7_MODREGS(tp), + { "ulprx", t7_ulp_rx_regs }, + { "ulptx", t7_ulp_tx_regs }, + { "pmrx", t7_pm_rx_regs }, + { "pmtx", t7_pm_tx_regs }, + T7_MODREGS(mps), + { "cplsw", t7_cpl_switch_regs }, + T7_MODREGS(smb), + { "i2c", t7_i2cm_regs }, + T7_MODREGS(mi), + T7_MODREGS(uart), + T7_MODREGS(pmu), + T7_MODREGS(sf), + T7_MODREGS(pl), + T7_MODREGS(le), + T7_MODREGS(ncsi), + { "mac", t7_mac_t7_regs }, + { "hma", t7_hma_t6_regs }, + { "crypto0", t7_crypto_0_regs }, + { "crypto1", t7_crypto_1_regs }, + { "cryptokey", t7_crypto_key_regs }, + T7_MODREGS(arm), + T7_MODREGS(gcache), + }; + + return dump_regs_table(argc, argv, regs, t7_mod, nitems(t7_mod)); +} +#undef T7_MODREGS + static int dump_regs_t4vf(int argc, const char *argv[], const uint32_t *regs) { @@ -478,6 +520,20 @@ dump_regs_t6vf(int argc, const char *argv[], const uint32_t *regs) return dump_regs_table(argc, argv, regs, t6vf_mod, nitems(t6vf_mod)); } +static int +dump_regs_t7vf(int argc, const char *argv[], const uint32_t *regs) +{ + static struct mod_regs t7vf_mod[] = { + { "sge", t5vf_sge_regs }, + { "mps", t4vf_mps_regs }, + { "pl", t7vf_pl_regs }, + { "mbdata", t4vf_mbdata_regs }, + { "cim", t4vf_cim_regs }, + }; + + return dump_regs_table(argc, argv, regs, t7vf_mod, nitems(t7vf_mod)); +} + static int dump_regs(int argc, const char *argv[]) { @@ -515,6 +571,11 @@ dump_regs(int argc, const char *argv[]) rc = dump_regs_t6vf(argc, argv, regs.data); else rc = dump_regs_t6(argc, argv, regs.data); + } else if (vers == 7) { + if (revision == 0x3f) + rc = dump_regs_t7vf(argc, argv, regs.data); + else + rc = dump_regs_t7(argc, argv, regs.data); } else { warnx("%s (type %d, rev %d) is not a known card.", g.nexus, vers, revision); @@ -1492,7 +1553,180 @@ show_struct(const uint32_t *words, int nwords, const struct field_desc *fd) #define FIELD1(name, start) FIELD(name, start, start) static void -show_t5t6_ctxt(const struct t4_sge_context *p, int vers) +show_t7_ctxt(const struct t4_sge_ctxt *p) +{ + static struct field_desc egress_t7[] = { + FIELD("uPToken_4k:", 197, 198), + FIELD("WrLength_5:", 196, 196), + FIELD("CpuId:", 193, 195), + FIELD("PCIeDataChannel_1:", 192, 192), + FIELD("DCA_ST:", 181, 191), + FIELD("StatusPgNS:", 180, 180), + FIELD("StatusPgRO:", 179, 179), + FIELD("FetchNS:", 178, 178), + FIELD("FetchRO:", 177, 177), + FIELD("Valid:", 176, 176), + FIELD("ReschedulePending_1:", 175, 175), + FIELD("PCIeDataChannel:", 174, 174), + FIELD("StatusPgTPHintEn:", 173, 173), + FIELD("StatusPgTPHint:", 171, 172), + FIELD("FetchTPHintEn:", 170, 170), + FIELD("FetchTPHint:", 168, 169), + FIELD("FCThreshOverride:", 167, 167), + { "WRLength:", 162, 166, 9, 0, 1 }, + FIELD("WRLengthKnown:", 161, 161), + FIELD("ReschedulePending:", 160, 160), + FIELD("TimerIx:", 157, 159), + FIELD("FetchBurstMin:", 156, 156), + FIELD("FLMPacking:", 155, 155), + FIELD("FetchBurstMax:", 153, 154), + FIELD("uPToken:", 133, 152), + FIELD("uPTokenEn:", 132, 132), + FIELD("UserModeIO:", 131, 131), + FIELD("uPFLCredits:", 123, 130), + FIELD("uPFLCreditEn:", 122, 122), + FIELD("FID:", 111, 121), + FIELD("HostFCMode:", 109, 110), + FIELD("HostFCOwner:", 108, 108), + { "CIDXFlushThresh:", 105, 107, 0, 0, 1 }, + FIELD("CIDX:", 89, 104), + FIELD("PIDX:", 73, 88), + { "BaseAddress:", 18, 72, 9, 1 }, + FIELD("QueueSize:", 2, 17), + FIELD("QueueType:", 1, 1), + FIELD("FetchSizeMode:", 0, 0), + { NULL } + }; + static struct field_desc fl_t7[] = { + FIELD("FLMcontextID_4k:", 197, 198), + FIELD("CpuId:", 193, 195), + FIELD("PCIeDataChannel_1:", 192, 192), + FIELD("DCA_ST:", 181, 191), + FIELD("StatusPgNS:", 180, 180), + FIELD("StatusPgRO:", 179, 179), + FIELD("FetchNS:", 178, 178), + FIELD("FetchRO:", 177, 177), + FIELD("Valid:", 176, 176), + FIELD("PCIeDataChannel:", 174, 175), + FIELD("StatusPgTPHintEn:", 173, 173), + FIELD("StatusPgTPHint:", 171, 172), + FIELD("FetchTPHintEn:", 170, 170), + FIELD("FetchTPHint:", 168, 169), + FIELD("FCThreshOverride:", 167, 167), + FIELD("ReschedulePending:", 160, 160), + FIELD("OnChipQueue:", 159, 159), + FIELD("FetchSizeMode:", 158, 158), + { "FetchBurstMin:", 156, 157, 4, 0, 1 }, + FIELD("FLMPacking:", 155, 155), + FIELD("FetchBurstMax:", 153, 154), + FIELD("FLMcongMode:", 152, 152), + FIELD("MaxuPFLCredits:", 144, 151), + FIELD("FLMcontextID:", 133, 143), + FIELD("uPTokenEn:", 132, 132), + FIELD("UserModeIO:", 131, 131), + FIELD("uPFLCredits:", 123, 130), + FIELD("uPFLCreditEn:", 122, 122), + FIELD("FID:", 111, 121), + FIELD("HostFCMode:", 109, 110), + FIELD("HostFCOwner:", 108, 108), + { "CIDXFlushThresh:", 105, 107, 0, 0, 1 }, + FIELD("CIDX:", 89, 104), + FIELD("PIDX:", 73, 88), + { "BaseAddress:", 18, 72, 9, 1 }, + FIELD("QueueSize:", 2, 17), + FIELD("QueueType:", 1, 1), + FIELD("CachePriority:", 0, 0), + { NULL } + }; + static struct field_desc ingress_t7[] = { + FIELD("Fid:", 171, 182), + FIELD("InterruptIDX4K:", 170, 170), + FIELD("CoalEn:", 169, 169), + FIELD("CoalAbort:", 168, 168), + FIELD("CoalCntr:", 161, 167), + FIELD("CoalCompTimerStatus:", 160, 160), + FIELD("CoalCompCntrStatus:", 159, 159), + FIELD("SP_NS:", 158, 158), + FIELD("SP_RO:", 157, 157), + FIELD("SP_TPHintEn:", 156, 156), + FIELD("SP_TPHint:", 154, 155), + FIELD("DCA_ST:", 143, 153), + FIELD("ISCSICoalescing:", 142, 142), + FIELD("Queue_Valid:", 141, 141), + FIELD("TimerPending:", 140, 140), + FIELD("DropRSS:", 139, 139), + FIELD("PCIeChannel:", 137, 138), + FIELD("SEInterruptArmed:", 136, 136), + FIELD("CongestionMgtEnable:", 135, 135), + FIELD("NoSnoop:", 134, 134), + FIELD("RelaxedOrdering:", 133, 133), + FIELD("GTSmode:", 132, 132), + FIELD("TPHintEn:", 131, 131), + FIELD("TPHint:", 129, 130), + FIELD("UpdateScheduling:", 128, 128), + FIELD("UpdateDelivery:", 126, 127), + FIELD("InterruptSent:", 125, 125), + FIELD("InterruptIDX:", 114, 124), + FIELD("InterruptDestination:", 113, 113), + FIELD("InterruptArmed:", 112, 112), + FIELD("RxIntCounter:", 106, 111), + FIELD("RxIntCounterThreshold:", 104, 105), + FIELD("Generation:", 103, 103), + { "BaseAddress:", 48, 102, 9, 1 }, + FIELD("PIDX:", 32, 47), + FIELD("CIDX:", 16, 31), + { "QueueSize:", 4, 15, 4, 0 }, + { "QueueEntrySize:", 2, 3, 4, 0, 1 }, + FIELD("QueueEntryOverride:", 1, 1), + FIELD("CachePriority:", 0, 0), + { NULL } + }; + static struct field_desc flm_t7[] = { + FIELD("MidCongEn:", 154, 154), + FIELD("FlPtr:", 90, 153), + FIELD("Valid:", 89, 89), + FIELD("SplitLenMode:", 87, 88), + FIELD("TPHintEn:", 86, 86), + FIELD("TPHint:", 84, 85), + FIELD("NoSnoop:", 83, 83), + FIELD("RelaxedOrdering:", 82, 82), + FIELD("DCA_ST:", 71, 81), + FIELD("EQid:", 54, 70), + FIELD("SplitEn:", 52, 53), + FIELD("PadEn:", 51, 51), + FIELD("PackEn:", 50, 50), + FIELD("Cache_Lock :", 49, 49), + FIELD("CongDrop:", 48, 48), + FIELD("Inflifght:", 47, 47), + FIELD("CongEn:", 46, 46), + FIELD("CongMode:", 45, 45), + FIELD("PackOffset:", 20, 39), + FIELD("CIDX:", 8, 15), + FIELD("PIDX:", 0, 7), + { NULL } + }; + static struct field_desc conm_t7[] = { + FIELD("CngMPSEnable:", 37, 37), + FIELD("CngTPMode:", 35, 36), + FIELD("CngDBPHdr:", 34, 34), + FIELD("CngDBPData:", 33, 33), + FIELD("CngIMSG:", 32, 32), + { "CngChMap:", 0, 31, 0, 1, 0 }, + { NULL } + }; + + if (p->mem_id == SGE_CONTEXT_EGRESS) + show_struct(p->data, 7, (p->data[0] & 2) ? fl_t7 : egress_t7); + else if (p->mem_id == SGE_CONTEXT_FLM) + show_struct(p->data, 5, flm_t7); + else if (p->mem_id == SGE_CONTEXT_INGRESS) + show_struct(p->data, 6, ingress_t7); + else if (p->mem_id == SGE_CONTEXT_CNM) + show_struct(p->data, 2, conm_t7); +} + +static void +show_t5t6_ctxt(const struct t4_sge_ctxt *p, int vers) { static struct field_desc egress_t5[] = { FIELD("DCA_ST:", 181, 191), @@ -1743,7 +1977,7 @@ show_t5t6_ctxt(const struct t4_sge_context *p, int vers) } static void -show_t4_ctxt(const struct t4_sge_context *p) +show_t4_ctxt(const struct t4_sge_ctxt *p) { static struct field_desc egress_t4[] = { FIELD1("StatusPgNS:", 180), @@ -1887,7 +2121,7 @@ get_sge_context(int argc, const char *argv[]) int rc; char *p; long cid; - struct t4_sge_context cntxt = {0}; + struct t4_sge_ctxt cntxt = {0}; if (argc != 2) { warnx("sge_context: incorrect number of arguments."); @@ -1915,14 +2149,21 @@ get_sge_context(int argc, const char *argv[]) } cntxt.cid = cid; - rc = doit(CHELSIO_T4_GET_SGE_CONTEXT, &cntxt); + rc = doit(CHELSIO_T4_GET_SGE_CTXT, &cntxt); if (rc != 0) return (rc); - if (g.chip_id == 4) + switch (g.chip_id) { + case 4: show_t4_ctxt(&cntxt); - else + break; + case 5: + case 6: show_t5t6_ctxt(&cntxt, g.chip_id); + break; + default: + show_t7_ctxt(&cntxt); + } return (0); } diff --git a/usr.sbin/cxgbetool/reg_defs_t4vf.c b/usr.sbin/cxgbetool/reg_defs_t4vf.c index 5ea7d4f276dd..bf60ee8a8356 100644 --- a/usr.sbin/cxgbetool/reg_defs_t4vf.c +++ b/usr.sbin/cxgbetool/reg_defs_t4vf.c @@ -122,6 +122,21 @@ struct reg_info t6vf_pl_regs[] = { { NULL, 0, 0 } }; +struct reg_info t7vf_pl_regs[] = { + { "PL_WHOAMI", 0x200, 0 }, + { "PortxMap", 24, 3 }, + { "SourceBus", 16, 2 }, + { "SourcePF", 9, 3 }, + { "IsVF", 8, 1 }, + { "VFID", 0, 8 }, + { "PL_VF_REV", 0x204, 0 }, + { "ChipID", 4, 4 }, + { "Rev", 0, 4 }, + { "PL_VF_REVISION", 0x208, 0 }, + + { NULL, 0, 0 } +}; + struct reg_info t4vf_cim_regs[] = { /* * Note: the Mailbox Control register has read side-effects so diff --git a/usr.sbin/cxgbetool/reg_defs_t7.c b/usr.sbin/cxgbetool/reg_defs_t7.c new file mode 100644 index 000000000000..549db9c546d5 --- /dev/null +++ b/usr.sbin/cxgbetool/reg_defs_t7.c @@ -0,0 +1,28216 @@ +/* This file is automatically generated --- changes will be lost */ +/* Generation Date : Thu Sep 11 05:26:14 PM IST 2025 */ +/* Directory name: t7_reg.txt, Changeset: 5945:1487219ecb20 */ + +struct reg_info t7_sge_regs[] = { + { "SGE_PF_KDOORBELL", 0x1e000, 0 }, + { "QID", 15, 17 }, + { "Sync", 14, 1 }, + { "Type", 13, 1 }, + { "PIDX", 0, 13 }, + { "SGE_PF_GTS", 0x1e004, 0 }, + { "IngressQID", 16, 16 }, + { "TimerReg", 13, 3 }, + { "SEIntArm", 12, 1 }, + { "CIDXInc", 0, 12 }, + { "SGE_PF_KTIMESTAMP_LO", 0x1e008, 0 }, + { "SGE_PF_KTIMESTAMP_HI", 0x1e00c, 0 }, + { "SGE_PF_KDOORBELL", 0x1e400, 0 }, + { "QID", 15, 17 }, + { "Sync", 14, 1 }, + { "Type", 13, 1 }, + { "PIDX", 0, 13 }, + { "SGE_PF_GTS", 0x1e404, 0 }, + { "IngressQID", 16, 16 }, + { "TimerReg", 13, 3 }, + { "SEIntArm", 12, 1 }, + { "CIDXInc", 0, 12 }, + { "SGE_PF_KTIMESTAMP_LO", 0x1e408, 0 }, + { "SGE_PF_KTIMESTAMP_HI", 0x1e40c, 0 }, + { "SGE_PF_KDOORBELL", 0x1e800, 0 }, + { "QID", 15, 17 }, + { "Sync", 14, 1 }, + { "Type", 13, 1 }, + { "PIDX", 0, 13 }, + { "SGE_PF_GTS", 0x1e804, 0 }, + { "IngressQID", 16, 16 }, + { "TimerReg", 13, 3 }, + { "SEIntArm", 12, 1 }, + { "CIDXInc", 0, 12 }, + { "SGE_PF_KTIMESTAMP_LO", 0x1e808, 0 }, + { "SGE_PF_KTIMESTAMP_HI", 0x1e80c, 0 }, + { "SGE_PF_KDOORBELL", 0x1ec00, 0 }, + { "QID", 15, 17 }, + { "Sync", 14, 1 }, + { "Type", 13, 1 }, + { "PIDX", 0, 13 }, + { "SGE_PF_GTS", 0x1ec04, 0 }, + { "IngressQID", 16, 16 }, + { "TimerReg", 13, 3 }, + { "SEIntArm", 12, 1 }, + { "CIDXInc", 0, 12 }, + { "SGE_PF_KTIMESTAMP_LO", 0x1ec08, 0 }, + { "SGE_PF_KTIMESTAMP_HI", 0x1ec0c, 0 }, + { "SGE_PF_KDOORBELL", 0x1f000, 0 }, + { "QID", 15, 17 }, + { "Sync", 14, 1 }, + { "Type", 13, 1 }, + { "PIDX", 0, 13 }, + { "SGE_PF_GTS", 0x1f004, 0 }, + { "IngressQID", 16, 16 }, + { "TimerReg", 13, 3 }, + { "SEIntArm", 12, 1 }, + { "CIDXInc", 0, 12 }, + { "SGE_PF_KTIMESTAMP_LO", 0x1f008, 0 }, + { "SGE_PF_KTIMESTAMP_HI", 0x1f00c, 0 }, + { "SGE_PF_KDOORBELL", 0x1f400, 0 }, + { "QID", 15, 17 }, + { "Sync", 14, 1 }, + { "Type", 13, 1 }, + { "PIDX", 0, 13 }, + { "SGE_PF_GTS", 0x1f404, 0 }, + { "IngressQID", 16, 16 }, + { "TimerReg", 13, 3 }, + { "SEIntArm", 12, 1 }, + { "CIDXInc", 0, 12 }, + { "SGE_PF_KTIMESTAMP_LO", 0x1f408, 0 }, + { "SGE_PF_KTIMESTAMP_HI", 0x1f40c, 0 }, + { "SGE_PF_KDOORBELL", 0x1f800, 0 }, + { "QID", 15, 17 }, + { "Sync", 14, 1 }, + { "Type", 13, 1 }, + { "PIDX", 0, 13 }, + { "SGE_PF_GTS", 0x1f804, 0 }, + { "IngressQID", 16, 16 }, + { "TimerReg", 13, 3 }, + { "SEIntArm", 12, 1 }, + { "CIDXInc", 0, 12 }, + { "SGE_PF_KTIMESTAMP_LO", 0x1f808, 0 }, + { "SGE_PF_KTIMESTAMP_HI", 0x1f80c, 0 }, + { "SGE_PF_KDOORBELL", 0x1fc00, 0 }, + { "QID", 15, 17 }, + { "Sync", 14, 1 }, + { "Type", 13, 1 }, + { "PIDX", 0, 13 }, + { "SGE_PF_GTS", 0x1fc04, 0 }, + { "IngressQID", 16, 16 }, + { "TimerReg", 13, 3 }, + { "SEIntArm", 12, 1 }, + { "CIDXInc", 0, 12 }, + { "SGE_PF_KTIMESTAMP_LO", 0x1fc08, 0 }, + { "SGE_PF_KTIMESTAMP_HI", 0x1fc0c, 0 }, + { "SGE_CONTROL", 0x1008, 0 }, + { "IgrAllCPLtoFL", 31, 1 }, + { "FLSplitMin", 22, 9 }, + { "NumOfFid", 19, 3 }, + { "RxPktCPLMode", 18, 1 }, + { "EgrStatusPageSize", 17, 1 }, + { "IngHintEnable2", 16, 1 }, + { "IngHintEnable1", 15, 1 }, + { "IngHintEnable0", 14, 1 }, + { "IngIntCompareIDX", 13, 1 }, + { "PktShift", 10, 3 }, + { "IngPCIeBoundary", 7, 3 }, + { "IngPadBoundary", 4, 3 }, + { "IngHintEnable3", 3, 1 }, + { "tf_mode", 1, 2 }, + { "GlobalEnable", 0, 1 }, + { "SGE_HOST_PAGE_SIZE", 0x100c, 0 }, + { "HostPageSizePF7", 28, 4 }, + { "HostPageSizePF6", 24, 4 }, + { "HostPageSizePF5", 20, 4 }, + { "HostPageSizePF4", 16, 4 }, + { "HostPageSizePF3", 12, 4 }, + { "HostPageSizePF2", 8, 4 }, + { "HostPageSizePF1", 4, 4 }, + { "HostPageSizePF0", 0, 4 }, + { "SGE_EGRESS_QUEUES_PER_PAGE_PF", 0x1010, 0 }, + { "QueuesPerPagePF7", 28, 4 }, + { "QueuesPerPagePF6", 24, 4 }, + { "QueuesPerPagePF5", 20, 4 }, + { "QueuesPerPagePF4", 16, 4 }, + { "QueuesPerPagePF3", 12, 4 }, + { "QueuesPerPagePF2", 8, 4 }, + { "QueuesPerPagePF1", 4, 4 }, + { "QueuesPerPagePF0", 0, 4 }, + { "SGE_EGRESS_QUEUES_PER_PAGE_VF", 0x1014, 0 }, + { "QueuesPerPageVFPF7", 28, 4 }, + { "QueuesPerPageVFPF6", 24, 4 }, + { "QueuesPerPageVFPF5", 20, 4 }, + { "QueuesPerPageVFPF4", 16, 4 }, + { "QueuesPerPageVFPF3", 12, 4 }, + { "QueuesPerPageVFPF2", 8, 4 }, + { "QueuesPerPageVFPF1", 4, 4 }, + { "QueuesPerPageVFPF0", 0, 4 }, + { "SGE_USER_MODE_LIMITS", 0x1018, 0 }, + { "Opcode_Min", 24, 8 }, + { "Opcode_Max", 16, 8 }, + { "Length_Min", 8, 8 }, + { "Length_Max", 0, 8 }, + { "SGE_WR_ERROR", 0x101c, 0 }, + { "WR_Sendpath_Error_Opcode", 16, 8 }, + { "WR_Sendpath_Opcode", 8, 8 }, + { "WR_Error_Opcode", 0, 8 }, + { "SGE_INT_CAUSE1", 0x1024, 0 }, + { "perr_flm_CreditFifo", 30, 1 }, + { "perr_imsg_hint_fifo", 29, 1 }, + { "perr_headersplit_fifo3", 28, 1 }, + { "perr_headersplit_fifo2", 27, 1 }, + { "perr_payload_fifo3", 26, 1 }, + { "perr_payload_fifo2", 25, 1 }, + { "perr_pc_rsp", 23, 1 }, + { "perr_pc_req", 22, 1 }, + { "perr_dbp_pc_rsp_fifo3", 21, 1 }, + { "perr_dbp_pc_rsp_fifo2", 20, 1 }, + { "perr_dbp_pc_rsp_fifo1", 19, 1 }, + { "perr_dbp_pc_rsp_fifo0", 18, 1 }, + { "perr_dmarbt", 17, 1 }, + { "perr_flm_DbpFifo", 16, 1 }, + { "perr_flm_MCReq_fifo", 15, 1 }, + { "perr_flm_HintFifo", 14, 1 }, + { "perr_align_ctl_fifo3", 13, 1 }, + { "perr_align_ctl_fifo2", 12, 1 }, + { "perr_align_ctl_fifo1", 11, 1 }, + { "perr_align_ctl_fifo0", 10, 1 }, + { "perr_edma_fifo3", 9, 1 }, + { "perr_edma_fifo2", 8, 1 }, + { "perr_edma_fifo1", 7, 1 }, + { "perr_edma_fifo0", 6, 1 }, + { "perr_pd_fifo3", 5, 1 }, + { "perr_pd_fifo2", 4, 1 }, + { "perr_pd_fifo1", 3, 1 }, + { "perr_pd_fifo0", 2, 1 }, + { "perr_ing_ctxt_mifrsp", 1, 1 }, + { "perr_egr_ctxt_mifrsp", 0, 1 }, + { "SGE_INT_ENABLE1", 0x1028, 0 }, + { "perr_flm_CreditFifo", 30, 1 }, + { "perr_imsg_hint_fifo", 29, 1 }, + { "perr_headersplit_fifo3", 28, 1 }, + { "perr_headersplit_fifo2", 27, 1 }, + { "perr_payload_fifo3", 26, 1 }, + { "perr_payload_fifo2", 25, 1 }, + { "perr_pc_rsp", 23, 1 }, + { "perr_pc_req", 22, 1 }, + { "perr_dbp_pc_rsp_fifo3", 21, 1 }, + { "perr_dbp_pc_rsp_fifo2", 20, 1 }, + { "perr_dbp_pc_rsp_fifo1", 19, 1 }, + { "perr_dbp_pc_rsp_fifo0", 18, 1 }, + { "perr_dmarbt", 17, 1 }, + { "perr_flm_DbpFifo", 16, 1 }, + { "perr_flm_MCReq_fifo", 15, 1 }, + { "perr_flm_HintFifo", 14, 1 }, + { "perr_align_ctl_fifo3", 13, 1 }, + { "perr_align_ctl_fifo2", 12, 1 }, + { "perr_align_ctl_fifo1", 11, 1 }, + { "perr_align_ctl_fifo0", 10, 1 }, + { "perr_edma_fifo3", 9, 1 }, + { "perr_edma_fifo2", 8, 1 }, + { "perr_edma_fifo1", 7, 1 }, + { "perr_edma_fifo0", 6, 1 }, + { "perr_pd_fifo3", 5, 1 }, + { "perr_pd_fifo2", 4, 1 }, + { "perr_pd_fifo1", 3, 1 }, + { "perr_pd_fifo0", 2, 1 }, + { "perr_ing_ctxt_mifrsp", 1, 1 }, + { "perr_egr_ctxt_mifrsp", 0, 1 }, + { "SGE_PERR_ENABLE1", 0x102c, 0 }, + { "perr_flm_CreditFifo", 30, 1 }, + { "perr_imsg_hint_fifo", 29, 1 }, + { "perr_headersplit_fifo3", 28, 1 }, + { "perr_headersplit_fifo2", 27, 1 }, + { "perr_payload_fifo3", 26, 1 }, + { "perr_payload_fifo2", 25, 1 }, + { "perr_pc_rsp", 23, 1 }, + { "perr_pc_req", 22, 1 }, + { "perr_dbp_pc_rsp_fifo3", 21, 1 }, + { "perr_dbp_pc_rsp_fifo2", 20, 1 }, + { "perr_dbp_pc_rsp_fifo1", 19, 1 }, + { "perr_dbp_pc_rsp_fifo0", 18, 1 }, + { "perr_dmarbt", 17, 1 }, + { "perr_flm_DbpFifo", 16, 1 }, + { "perr_flm_MCReq_fifo", 15, 1 }, + { "perr_flm_HintFifo", 14, 1 }, + { "perr_align_ctl_fifo3", 13, 1 }, + { "perr_align_ctl_fifo2", 12, 1 }, + { "perr_align_ctl_fifo1", 11, 1 }, + { "perr_align_ctl_fifo0", 10, 1 }, + { "perr_edma_fifo3", 9, 1 }, + { "perr_edma_fifo2", 8, 1 }, + { "perr_edma_fifo1", 7, 1 }, + { "perr_edma_fifo0", 6, 1 }, + { "perr_pd_fifo3", 5, 1 }, + { "perr_pd_fifo2", 4, 1 }, + { "perr_pd_fifo1", 3, 1 }, + { "perr_pd_fifo0", 2, 1 }, + { "perr_ing_ctxt_mifrsp", 1, 1 }, + { "perr_egr_ctxt_mifrsp", 0, 1 }, + { "SGE_INT_CAUSE2", 0x1030, 0 }, + { "tf_fifo_perr", 24, 1 }, + { "perr_egr_dbp_tx_coal", 23, 1 }, + { "perr_dbp_fl_fifo", 22, 1 }, + { "deq_ll_perr", 21, 1 }, + { "enq_perr", 20, 1 }, + { "deq_out_perr", 19, 1 }, + { "buf_perr", 18, 1 }, + { "perr_isw_idma3_fifo", 15, 1 }, + { "perr_conm_sram", 14, 1 }, + { "perr_isw_idma2_fifo", 13, 1 }, + { "perr_isw_idma0_fifo", 12, 1 }, + { "perr_isw_idma1_fifo", 11, 1 }, + { "perr_isw_dbp_fifo", 10, 1 }, + { "perr_isw_gts_fifo", 9, 1 }, + { "perr_itp_evr", 8, 1 }, + { "perr_flm_cntxmem", 7, 1 }, + { "perr_flm_l1Cache", 6, 1 }, + { "sge_ipp_fifo_perr", 5, 1 }, + { "perr_dbp_hp_fifo", 4, 1 }, + { "perr_db_fifo", 3, 1 }, + { "perr_ing_ctxt_cache", 2, 1 }, + { "perr_egr_ctxt_cache", 1, 1 }, + { "perr_base_size", 0, 1 }, + { "SGE_INT_ENABLE2", 0x1034, 0 }, + { "tf_fifo_perr", 24, 1 }, + { "perr_egr_dbp_tx_coal", 23, 1 }, + { "perr_dbp_fl_fifo", 22, 1 }, + { "deq_ll_perr", 21, 1 }, + { "enq_perr", 20, 1 }, + { "deq_out_perr", 19, 1 }, + { "buf_perr", 18, 1 }, + { "perr_isw_idma3_fifo", 15, 1 }, + { "perr_conm_sram", 14, 1 }, + { "perr_isw_idma2_fifo", 13, 1 }, + { "perr_isw_idma0_fifo", 12, 1 }, + { "perr_isw_idma1_fifo", 11, 1 }, + { "perr_isw_dbp_fifo", 10, 1 }, + { "perr_isw_gts_fifo", 9, 1 }, + { "perr_itp_evr", 8, 1 }, + { "perr_flm_cntxmem", 7, 1 }, + { "perr_flm_l1Cache", 6, 1 }, + { "sge_ipp_fifo_perr", 5, 1 }, + { "perr_dbp_hp_fifo", 4, 1 }, + { "perr_db_fifo", 3, 1 }, + { "perr_ing_ctxt_cache", 2, 1 }, + { "perr_egr_ctxt_cache", 1, 1 }, + { "perr_base_size", 0, 1 }, + { "SGE_PERR_ENABLE2", 0x1038, 0 }, + { "tf_fifo_perr", 24, 1 }, + { "perr_egr_dbp_tx_coal", 23, 1 }, + { "perr_dbp_fl_fifo", 22, 1 }, + { "deq_ll_perr", 21, 1 }, + { "enq_perr", 20, 1 }, + { "deq_out_perr", 19, 1 }, + { "buf_perr", 18, 1 }, + { "perr_isw_idma3_fifo", 15, 1 }, + { "perr_conm_sram", 14, 1 }, + { "perr_isw_idma2_fifo", 13, 1 }, + { "perr_isw_idma0_fifo", 12, 1 }, + { "perr_isw_idma1_fifo", 11, 1 }, + { "perr_isw_dbp_fifo", 10, 1 }, + { "perr_isw_gts_fifo", 9, 1 }, + { "perr_itp_evr", 8, 1 }, + { "perr_flm_cntxmem", 7, 1 }, + { "perr_flm_l1Cache", 6, 1 }, + { "sge_ipp_fifo_perr", 5, 1 }, + { "perr_dbp_hp_fifo", 4, 1 }, + { "perr_dbp_lp_fifo", 3, 1 }, + { "perr_ing_ctxt_cache", 2, 1 }, + { "perr_egr_ctxt_cache", 1, 1 }, + { "perr_base_size", 0, 1 }, + { "SGE_INT_CAUSE3", 0x103c, 0 }, + { "err_flm_dbp", 31, 1 }, + { "err_flm_idma1", 30, 1 }, + { "err_flm_idma0", 29, 1 }, + { "err_flm_hint", 28, 1 }, + { "err_pcie_error3", 27, 1 }, + { "err_pcie_error2", 26, 1 }, + { "err_pcie_error1", 25, 1 }, + { "err_pcie_error0", 24, 1 }, + { "err_timer_above_max_qid", 23, 1 }, + { "err_cpl_exceed_iqe_size", 22, 1 }, + { "err_invalid_cidx_inc", 21, 1 }, + { "err_itp_time_paused", 20, 1 }, + { "err_cpl_opcode_0", 19, 1 }, + { "err_dropped_db", 18, 1 }, + { "err_data_cpl_on_high_qid1", 17, 1 }, + { "err_data_cpl_on_high_qid0", 16, 1 }, + { "err_bad_db_pidx3", 15, 1 }, + { "err_bad_db_pidx2", 14, 1 }, + { "err_bad_db_pidx1", 13, 1 }, + { "err_bad_db_pidx0", 12, 1 }, + { "err_ing_pcie_chan", 11, 1 }, + { "err_ing_ctxt_prio", 10, 1 }, + { "err_egr_ctxt_prio", 9, 1 }, + { "dbp_tbuf_full", 8, 1 }, + { "fatal_wre_len", 7, 1 }, + { "reg_address_err", 6, 1 }, + { "ingress_size_err", 5, 1 }, + { "egress_size_err", 4, 1 }, + { "err_inv_ctxt3", 3, 1 }, + { "err_inv_ctxt2", 2, 1 }, + { "err_inv_ctxt1", 1, 1 }, + { "err_inv_ctxt0", 0, 1 }, + { "SGE_INT_ENABLE3", 0x1040, 0 }, + { "err_flm_dbp", 31, 1 }, + { "err_flm_idma1", 30, 1 }, + { "err_flm_idma0", 29, 1 }, + { "err_flm_hint", 28, 1 }, + { "err_pcie_error3", 27, 1 }, + { "err_pcie_error2", 26, 1 }, + { "err_pcie_error1", 25, 1 }, + { "err_pcie_error0", 24, 1 }, + { "err_timer_above_max_qid", 23, 1 }, + { "err_cpl_exceed_iqe_size", 22, 1 }, + { "err_invalid_cidx_inc", 21, 1 }, + { "err_itp_time_paused", 20, 1 }, + { "err_cpl_opcode_0", 19, 1 }, + { "err_dropped_db", 18, 1 }, + { "err_data_cpl_on_high_qid1", 17, 1 }, + { "err_data_cpl_on_high_qid0", 16, 1 }, + { "err_bad_db_pidx3", 15, 1 }, + { "err_bad_db_pidx2", 14, 1 }, + { "err_bad_db_pidx1", 13, 1 }, + { "err_bad_db_pidx0", 12, 1 }, + { "err_ing_pcie_chan", 11, 1 }, + { "err_ing_ctxt_prio", 10, 1 }, + { "err_egr_ctxt_prio", 9, 1 }, + { "dbp_tbuf_full", 8, 1 }, + { "fatal_wre_len", 7, 1 }, + { "reg_address_err", 6, 1 }, + { "ingress_size_err", 5, 1 }, + { "egress_size_err", 4, 1 }, + { "err_inv_ctxt3", 3, 1 }, + { "err_inv_ctxt2", 2, 1 }, + { "err_inv_ctxt1", 1, 1 }, + { "err_inv_ctxt0", 0, 1 }, + { "SGE_FL_BUFFER_SIZE0", 0x1044, 0 }, + { "Size", 4, 20 }, + { "SGE_FL_BUFFER_SIZE1", 0x1048, 0 }, + { "Size", 4, 20 }, + { "SGE_FL_BUFFER_SIZE2", 0x104c, 0 }, + { "Size", 4, 20 }, + { "SGE_FL_BUFFER_SIZE3", 0x1050, 0 }, + { "Size", 4, 20 }, + { "SGE_FL_BUFFER_SIZE4", 0x1054, 0 }, + { "Size", 4, 20 }, + { "SGE_FL_BUFFER_SIZE5", 0x1058, 0 }, + { "Size", 4, 20 }, + { "SGE_FL_BUFFER_SIZE6", 0x105c, 0 }, + { "Size", 4, 20 }, + { "SGE_FL_BUFFER_SIZE7", 0x1060, 0 }, + { "Size", 4, 20 }, + { "SGE_FL_BUFFER_SIZE8", 0x1064, 0 }, + { "Size", 4, 20 }, + { "SGE_FL_BUFFER_SIZE9", 0x1068, 0 }, + { "Size", 4, 20 }, + { "SGE_FL_BUFFER_SIZE10", 0x106c, 0 }, + { "Size", 4, 20 }, + { "SGE_FL_BUFFER_SIZE11", 0x1070, 0 }, + { "Size", 4, 20 }, + { "SGE_FL_BUFFER_SIZE12", 0x1074, 0 }, + { "Size", 4, 20 }, + { "SGE_FL_BUFFER_SIZE13", 0x1078, 0 }, + { "Size", 4, 20 }, + { "SGE_FL_BUFFER_SIZE14", 0x107c, 0 }, + { "Size", 4, 20 }, + { "SGE_FL_BUFFER_SIZE15", 0x1080, 0 }, + { "Size", 4, 20 }, + { "SGE_DBQ_CTXT_BADDR", 0x1084, 0 }, + { "BaseAddr", 3, 29 }, + { "SGE_IMSG_CTXT_BADDR", 0x1088, 0 }, + { "BaseAddr", 3, 29 }, + { "SGE_FLM_CACHE_BADDR", 0x108c, 0 }, + { "BaseAddr", 3, 29 }, + { "SGE_FLM_CFG", 0x1090, 0 }, + { "OpMode", 26, 6 }, + { "NullPtr", 20, 4 }, + { "NullPtrEn", 19, 1 }, + { "NoHdr", 18, 1 }, + { "CachePtrCnt", 16, 2 }, + { "EDRAMPtrCnt", 14, 2 }, + { "HdrStartFLQ", 11, 3 }, + { "FetchThresh", 6, 5 }, + { "CreditCnt", 4, 2 }, + { "CreditCntPacking", 2, 2 }, + { "HdrStartFLQ4K", 1, 1 }, + { "NoEDRAM", 0, 1 }, + { "SGE_CONM_CTRL", 0x1094, 0 }, + { "EgrThresholdPacking", 16, 8 }, + { "EgrThreshold", 8, 8 }, + { "IngThreshold", 2, 6 }, + { "SGE_TIMESTAMP_LO", 0x1098, 0 }, + { "SGE_TIMESTAMP_HI", 0x109c, 0 }, + { "Opcode", 28, 2 }, + { "Value", 0, 28 }, + { "SGE_INGRESS_RX_THRESHOLD", 0x10a0, 0 }, + { "Threshold_0", 24, 6 }, + { "Threshold_1", 16, 6 }, + { "Threshold_2", 8, 6 }, + { "Threshold_3", 0, 6 }, + { "SGE_DBFIFO_STATUS", 0x10a4, 0 }, + { "vfifo_cnt", 15, 17 }, + { "coal_ctl_fifo_cnt", 8, 6 }, + { "merge_fifo_cnt", 0, 6 }, + { "SGE_DOORBELL_CONTROL", 0x10a8, 0 }, + { "HintDepthCtl", 27, 5 }, + { "NoCoalesce", 26, 1 }, + { "HP_Weight", 24, 2 }, + { "HP_Disable", 23, 1 }, + { "ForceUserDBtoLP", 22, 1 }, + { "ForceVFPF0DBtoLP", 21, 1 }, + { "ForceVFPF1DBtoLP", 20, 1 }, + { "ForceVFPF2DBtoLP", 19, 1 }, + { "ForceVFPF3DBtoLP", 18, 1 }, + { "ForceVFPF4DBtoLP", 17, 1 }, + { "ForceVFPF5DBtoLP", 16, 1 }, + { "ForceVFPF6DBtoLP", 15, 1 }, + { "ForceVFPF7DBtoLP", 14, 1 }, + { "Enable_Drop", 13, 1 }, + { "Drop_Timeout", 7, 6 }, + { "InvOnDBSync", 6, 1 }, + { "InvOnGTSSync", 5, 1 }, + { "db_dbg_en", 4, 1 }, + { "gts_dbg_timer_reg", 1, 3 }, + { "gts_dbg_en", 0, 1 }, + { "SGE_ITP_CONTROL", 0x10b4, 0 }, + { "TScale", 28, 4 }, + { "Critical_Time", 10, 15 }, + { "LL_Empty", 4, 6 }, + { "LL_Read_Wait_Disable", 0, 1 }, + { "SGE_TIMER_VALUE_0_AND_1", 0x10b8, 0 }, + { "TimerValue0", 16, 16 }, + { "TimerValue1", 0, 16 }, + { "SGE_TIMER_VALUE_2_AND_3", 0x10bc, 0 }, + { "TimerValue2", 16, 16 }, + { "TimerValue3", 0, 16 }, + { "SGE_TIMER_VALUE_4_AND_5", 0x10c0, 0 }, + { "TimerValue4", 16, 16 }, + { "TimerValue5", 0, 16 }, + { "SGE_GK_CONTROL", 0x10c4, 0 }, + { "en_flm_fifth", 29, 1 }, + { "fl_prog_thresh", 20, 9 }, + { "coal_all_thread", 19, 1 }, + { "en_pshb", 18, 1 }, + { "en_db_fifth", 17, 1 }, + { "db_prog_thresh", 8, 9 }, + { "100ns_timer", 0, 8 }, + { "SGE_GK_CONTROL2", 0x10c8, 0 }, + { "dbq_timer_tick", 16, 16 }, + { "fl_merge_cnt_thresh", 8, 4 }, + { "merge_cnt_thresh", 0, 6 }, + { "SGE_DEBUG_INDEX", 0x10cc, 0 }, + { "SGE_DEBUG_DATA_HIGH", 0x10d0, 0 }, + { "SGE_DEBUG_DATA_LOW", 0x10d4, 0 }, + { "SGE_REVISION", 0x10d8, 0 }, + { "SGE_INT_CAUSE4", 0x10dc, 0 }, + { "err_ishift_ur1", 31, 1 }, + { "err_ishift_ur0", 30, 1 }, + { "bar2_egress_len_or_addr_err", 29, 1 }, + { "err_cpl_exceed_max_iqe_size1", 28, 1 }, + { "err_cpl_exceed_max_iqe_size0", 27, 1 }, + { "err_wr_len_too_large3", 26, 1 }, + { "err_wr_len_too_large2", 25, 1 }, + { "err_wr_len_too_large1", 24, 1 }, + { "err_wr_len_too_large0", 23, 1 }, + { "err_large_minfetch_with_txcoal3", 22, 1 }, + { "err_large_minfetch_with_txcoal2", 21, 1 }, + { "err_large_minfetch_with_txcoal1", 20, 1 }, + { "err_large_minfetch_with_txcoal0", 19, 1 }, + { "coal_with_hp_disable_err", 18, 1 }, + { "bar2_egress_coal0_err", 17, 1 }, + { "bar2_egress_size_err", 16, 1 }, + { "flm_pc_rsp_err", 15, 1 }, + { "err_th3_max_fetch", 14, 1 }, + { "err_th2_max_fetch", 13, 1 }, + { "err_th1_max_fetch", 12, 1 }, + { "err_th0_max_fetch", 11, 1 }, + { "err_rx_cpl_packet_size1", 10, 1 }, + { "err_rx_cpl_packet_size0", 9, 1 }, + { "err_bad_upfl_inc_credit3", 8, 1 }, + { "err_bad_upfl_inc_credit2", 7, 1 }, + { "err_bad_upfl_inc_credit1", 6, 1 }, + { "err_bad_upfl_inc_credit0", 5, 1 }, + { "err_physaddr_len0_idma1", 4, 1 }, + { "err_physaddr_len0_idma0", 3, 1 }, + { "err_flm_invalid_pkt_drop1", 2, 1 }, + { "err_flm_invalid_pkt_drop0", 1, 1 }, + { "err_unexpected_timer", 0, 1 }, + { "SGE_INT_ENABLE4", 0x10e0, 0 }, + { "err_ishift_ur1", 31, 1 }, + { "err_ishift_ur0", 30, 1 }, + { "bar2_egress_len_or_addr_err", 29, 1 }, + { "err_cpl_exceed_max_iqe_size1", 28, 1 }, + { "err_cpl_exceed_max_iqe_size0", 27, 1 }, + { "err_wr_len_too_large3", 26, 1 }, + { "err_wr_len_too_large2", 25, 1 }, + { "err_wr_len_too_large1", 24, 1 }, + { "err_wr_len_too_large0", 23, 1 }, + { "err_large_minfetch_with_txcoal3", 22, 1 }, + { "err_large_minfetch_with_txcoal2", 21, 1 }, + { "err_large_minfetch_with_txcoal1", 20, 1 }, + { "err_large_minfetch_with_txcoal0", 19, 1 }, + { "coal_with_hp_disable_err", 18, 1 }, + { "bar2_egress_coal0_err", 17, 1 }, + { "bar2_egress_size_err", 16, 1 }, + { "flm_pc_rsp_err", 15, 1 }, + { "err_th3_max_fetch", 14, 1 }, + { "err_th2_max_fetch", 13, 1 }, + { "err_th1_max_fetch", 12, 1 }, + { "err_th0_max_fetch", 11, 1 }, + { "err_rx_cpl_packet_size1", 10, 1 }, + { "err_rx_cpl_packet_size0", 9, 1 }, + { "err_bad_upfl_inc_credit3", 8, 1 }, + { "err_bad_upfl_inc_credit2", 7, 1 }, + { "err_bad_upfl_inc_credit1", 6, 1 }, + { "err_bad_upfl_inc_credit0", 5, 1 }, + { "err_physaddr_len0_idma1", 4, 1 }, + { "err_physaddr_len0_idma0", 3, 1 }, + { "err_flm_invalid_pkt_drop1", 2, 1 }, + { "err_flm_invalid_pkt_drop0", 1, 1 }, + { "err_unexpected_timer", 0, 1 }, + { "SGE_STAT_TOTAL", 0x10e4, 0 }, + { "SGE_STAT_MATCH", 0x10e8, 0 }, + { "SGE_STAT_CFG", 0x10ec, 0 }, + { "StatSource", 9, 4 }, + { "ITPOpMode", 8, 1 }, + { "EgrCtxtOpMode", 6, 2 }, + { "IngCtxtOpMode", 4, 2 }, + { "StatMode", 0, 4 }, + { "SGE_HINT_CFG", 0x10f0, 0 }, + { "uPCutoffThreshLp", 12, 11 }, + { "HintsAllowedNoHdr", 6, 6 }, + { "HintsAllowedHdr", 0, 6 }, + { "SGE_INGRESS_QUEUES_PER_PAGE_PF", 0x10f4, 0 }, + { "QueuesPerPagePF7", 28, 4 }, + { "QueuesPerPagePF6", 24, 4 }, + { "QueuesPerPagePF5", 20, 4 }, + { "QueuesPerPagePF4", 16, 4 }, + { "QueuesPerPagePF3", 12, 4 }, + { "QueuesPerPagePF2", 8, 4 }, *** 29611 LINES SKIPPED ***
