The branch main has been updated by np: URL: https://cgit.FreeBSD.org/src/commit/?id=e5ce2d39368f702cc910e3baf103df0a6e1f9266
commit e5ce2d39368f702cc910e3baf103df0a6e1f9266 Author: Navdeep Parhar <[email protected]> AuthorDate: 2025-09-29 13:50:34 +0000 Commit: Navdeep Parhar <[email protected]> CommitDate: 2025-09-29 14:26:01 +0000 libcxgb4: Get userspace RDMA tools to recognize T7 based RNICs MFC after: 3 days Sponsored by: Chelsio Communications --- contrib/ofed/libcxgb4/dev.c | 9 ++++++++- contrib/ofed/libcxgb4/libcxgb4.h | 5 +++++ contrib/ofed/libcxgb4/t4_chip_type.h | 10 ++++++++++ contrib/ofed/libcxgb4/t4_pci_id_tbl.h | 27 +++++++++++++++++++++------ 4 files changed, 44 insertions(+), 7 deletions(-) diff --git a/contrib/ofed/libcxgb4/dev.c b/contrib/ofed/libcxgb4/dev.c index d3c289dad9f2..db728f5627da 100644 --- a/contrib/ofed/libcxgb4/dev.c +++ b/contrib/ofed/libcxgb4/dev.c @@ -144,6 +144,8 @@ static struct ibv_context *c4iw_alloc_context(struct ibv_device *ibdev, context->ibv_ctx.ops = c4iw_ctx_ops; switch (rhp->chip_version) { + case CHELSIO_T7: + PDBG("%s T7/T6/T5/T4 device\n", __FUNCTION__); case CHELSIO_T6: PDBG("%s T6/T5/T4 device\n", __FUNCTION__); case CHELSIO_T5: @@ -429,6 +431,8 @@ static struct verbs_device *cxgb4_driver_init(const char *uverbs_sys_path, strstr(&ibdev[2], "nex") && devnum >= 0) { snprintf(dev_str, sizeof(dev_str), "/dev/t%cnex/%d", ibdev[1], devnum); + } else if (strstr(&ibdev[0], "chnex") && devnum >= 0) { + snprintf(dev_str, sizeof(dev_str), "/dev/chnex/%d", devnum); } else return NULL; @@ -523,7 +527,10 @@ found: goto err; dev->ibv_dev.ops = &c4iw_dev_ops; - dev->chip_version = CHELSIO_CHIP_VERSION(hca_table[i].device >> 8); + if (hca_table[i].device == 0xd000) + dev->chip_version = CHELSIO_T7; + else + dev->chip_version = CHELSIO_CHIP_VERSION(hca_table[i].device >> 8); dev->abi_version = abi_version; PDBG("%s device claimed\n", __FUNCTION__); diff --git a/contrib/ofed/libcxgb4/libcxgb4.h b/contrib/ofed/libcxgb4/libcxgb4.h index b891e8b1df97..216eee05a9d8 100644 --- a/contrib/ofed/libcxgb4/libcxgb4.h +++ b/contrib/ofed/libcxgb4/libcxgb4.h @@ -64,6 +64,11 @@ struct c4iw_dev { int abi_version; }; +static inline int dev_is_t7(struct c4iw_dev *dev) +{ + return dev->chip_version == CHELSIO_T7; +} + static inline int dev_is_t6(struct c4iw_dev *dev) { return dev->chip_version == CHELSIO_T6; diff --git a/contrib/ofed/libcxgb4/t4_chip_type.h b/contrib/ofed/libcxgb4/t4_chip_type.h index 54b718111e3f..ae3b760c51a1 100644 --- a/contrib/ofed/libcxgb4/t4_chip_type.h +++ b/contrib/ofed/libcxgb4/t4_chip_type.h @@ -37,6 +37,7 @@ #define CHELSIO_T4 0x4 #define CHELSIO_T5 0x5 #define CHELSIO_T6 0x6 +#define CHELSIO_T7 0x7 /* We code the Chelsio T4 Family "Chip Code" as a tuple: * @@ -65,6 +66,10 @@ enum chip_type { T6_A0 = CHELSIO_CHIP_CODE(CHELSIO_T6, 0), T6_FIRST_REV = T6_A0, T6_LAST_REV = T6_A0, + + T7_A1 = CHELSIO_CHIP_CODE(CHELSIO_T7, 1), + T7_FIRST_REV = T7_A1, + T7_LAST_REV = T7_A1, }; static inline int is_t4(enum chip_type chip) @@ -82,4 +87,9 @@ static inline int is_t6(enum chip_type chip) return (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T6); } +static inline int is_t7(enum chip_type chip) +{ + return (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T7); +} + #endif /* __T4_CHIP_TYPE_H__ */ diff --git a/contrib/ofed/libcxgb4/t4_pci_id_tbl.h b/contrib/ofed/libcxgb4/t4_pci_id_tbl.h index 50812a1d67bd..0ff7e689dc84 100644 --- a/contrib/ofed/libcxgb4/t4_pci_id_tbl.h +++ b/contrib/ofed/libcxgb4/t4_pci_id_tbl.h @@ -92,8 +92,7 @@ #endif CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN - /* T4 adapters: - */ + /* T4 adapters */ CH_PCI_ID_TABLE_FENTRY(0x4000), /* T440-dbg */ CH_PCI_ID_TABLE_FENTRY(0x4001), /* T420-cr */ CH_PCI_ID_TABLE_FENTRY(0x4002), /* T422-cr */ @@ -119,8 +118,7 @@ CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN CH_PCI_ID_TABLE_FENTRY(0x4087), /* Custom T440-cr */ CH_PCI_ID_TABLE_FENTRY(0x4088), /* Custom T440 2-xaui, 2-xfi */ - /* T5 adapters: - */ + /* T5 adapters */ CH_PCI_ID_TABLE_FENTRY(0x5000), /* T580-dbg */ CH_PCI_ID_TABLE_FENTRY(0x5001), /* T520-cr */ CH_PCI_ID_TABLE_FENTRY(0x5002), /* T522-cr */ @@ -169,8 +167,7 @@ CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN CH_PCI_ID_TABLE_FENTRY(0x509b), /* Custom T540-CR LOM */ CH_PCI_ID_TABLE_FENTRY(0x509c), /* Custom T520-CR*/ - /* T6 adapters: - */ + /* T6 adapters */ CH_PCI_ID_TABLE_FENTRY(0x6001), CH_PCI_ID_TABLE_FENTRY(0x6002), CH_PCI_ID_TABLE_FENTRY(0x6003), @@ -184,6 +181,24 @@ CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN CH_PCI_ID_TABLE_FENTRY(0x6011), CH_PCI_ID_TABLE_FENTRY(0x6014), CH_PCI_ID_TABLE_FENTRY(0x6015), + CH_PCI_ID_TABLE_FENTRY(0x6081), + + /* T7 adapters */ + { .vendor = 0x1425, .device = 0xd000 }, /* T7 FPGA */ + CH_PCI_ID_TABLE_FENTRY(0x7000), /* T7-DBG */ + CH_PCI_ID_TABLE_FENTRY(0x7001), /* T7250 */ + CH_PCI_ID_TABLE_FENTRY(0x7002), /* S7250 */ + CH_PCI_ID_TABLE_FENTRY(0x7003), /* T7450 */ + CH_PCI_ID_TABLE_FENTRY(0x7004), /* S7450 */ + CH_PCI_ID_TABLE_FENTRY(0x7005), /* T72200 */ + CH_PCI_ID_TABLE_FENTRY(0x7006), /* S72200 */ + CH_PCI_ID_TABLE_FENTRY(0x7007), /* T72200-FH */ + CH_PCI_ID_TABLE_FENTRY(0x7008), /* T71400 */ + CH_PCI_ID_TABLE_FENTRY(0x7009), /* S7210-BT */ + CH_PCI_ID_TABLE_FENTRY(0x700a), /* T7450-RC */ + CH_PCI_ID_TABLE_FENTRY(0x700b), /* T72200-RC */ + CH_PCI_ID_TABLE_FENTRY(0x700c), /* T72200-FH-RC */ + CH_PCI_ID_TABLE_FENTRY(0x7080), /* Custom */ CH_PCI_DEVICE_ID_TABLE_DEFINE_END; #endif /* __T4_PCI_ID_TBL_H__ */
