The branch main has been updated by np: URL: https://cgit.FreeBSD.org/src/commit/?id=c392b5a9e44b9c8a0173a4e2c1fb87ee88f4aa3f
commit c392b5a9e44b9c8a0173a4e2c1fb87ee88f4aa3f Author: Navdeep Parhar <[email protected]> AuthorDate: 2025-09-29 08:43:28 +0000 Commit: Navdeep Parhar <[email protected]> CommitDate: 2025-09-29 14:25:59 +0000 cxgbe(4): Congestion manager context settings for T7 MFC after: 3 days Sponsored by: Chelsio Communications --- sys/dev/cxgbe/t4_netmap.c | 7 +++++-- sys/dev/cxgbe/t4_sge.c | 27 +++++++++++++++++++-------- 2 files changed, 24 insertions(+), 10 deletions(-) diff --git a/sys/dev/cxgbe/t4_netmap.c b/sys/dev/cxgbe/t4_netmap.c index ddd7d974aa48..12aaca6ee77a 100644 --- a/sys/dev/cxgbe/t4_netmap.c +++ b/sys/dev/cxgbe/t4_netmap.c @@ -276,7 +276,7 @@ free_nm_txq(struct vi_info *vi, struct sge_nm_txq *nm_txq) static int alloc_nm_rxq_hwq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq) { - int rc, cntxt_id; + int rc, cntxt_id, cong_map; __be32 v; struct adapter *sc = vi->adapter; struct port_info *pi = vi->pi; @@ -284,7 +284,6 @@ alloc_nm_rxq_hwq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq) struct netmap_adapter *na = NA(vi->ifp); struct fw_iq_cmd c; const int cong_drop = nm_cong_drop; - const int cong_map = pi->rx_e_chan_map; MPASS(na != NULL); MPASS(nm_rxq->iq_desc != NULL); @@ -321,6 +320,10 @@ alloc_nm_rxq_hwq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq) c.iqsize = htobe16(vi->qsize_rxq); c.iqaddr = htobe64(nm_rxq->iq_ba); if (cong_drop != -1) { + if (chip_id(sc) >= CHELSIO_T7) + cong_map = 1 << pi->hw_port; + else + cong_map = pi->rx_e_chan_map; c.iqns_to_fl0congen = htobe32(F_FW_IQ_CMD_IQFLINTCONGEN | V_FW_IQ_CMD_FL0CNGCHMAP(cong_map) | F_FW_IQ_CMD_FL0CONGCIF | F_FW_IQ_CMD_FL0CONGEN); diff --git a/sys/dev/cxgbe/t4_sge.c b/sys/dev/cxgbe/t4_sge.c index 4aa2b7236979..ce506f6c9192 100644 --- a/sys/dev/cxgbe/t4_sge.c +++ b/sys/dev/cxgbe/t4_sge.c @@ -3586,7 +3586,13 @@ alloc_iq_fl_hwq(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl) c.iqaddr = htobe64(iq->ba); c.iqns_to_fl0congen = htobe32(V_FW_IQ_CMD_IQTYPE(iq->qtype)); if (iq->cong_drop != -1) { - cong_map = iq->qtype == IQ_ETH ? pi->rx_e_chan_map : 0; + if (iq->qtype == IQ_ETH) { + if (chip_id(sc) >= CHELSIO_T7) + cong_map = 1 << pi->hw_port; + else + cong_map = pi->rx_e_chan_map; + } else + cong_map = 0; c.iqns_to_fl0congen |= htobe32(F_FW_IQ_CMD_IQFLINTCONGEN); } @@ -3939,14 +3945,19 @@ t4_sge_set_conm_context(struct adapter *sc, int cntxt_id, int cong_drop, param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) | V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) | V_FW_PARAMS_PARAM_YZ(cntxt_id); - val = V_CONMCTXT_CNGTPMODE(cong_mode); - if (cong_mode == X_CONMCTXT_CNGTPMODE_CHANNEL || - cong_mode == X_CONMCTXT_CNGTPMODE_BOTH) { - for (i = 0, ch_map = 0; i < 4; i++) { - if (cong_map & (1 << i)) - ch_map |= 1 << (i << cng_ch_bits_log); + if (chip_id(sc) >= CHELSIO_T7) { + val = V_T7_DMAQ_CONM_CTXT_CNGTPMODE(cong_mode) | + V_T7_DMAQ_CONM_CTXT_CH_VEC(cong_map); + } else { + val = V_CONMCTXT_CNGTPMODE(cong_mode); + if (cong_mode == X_CONMCTXT_CNGTPMODE_CHANNEL || + cong_mode == X_CONMCTXT_CNGTPMODE_BOTH) { + for (i = 0, ch_map = 0; i < 4; i++) { + if (cong_map & (1 << i)) + ch_map |= 1 << (i << cng_ch_bits_log); + } + val |= V_CONMCTXT_CNGCHMAP(ch_map); } - val |= V_CONMCTXT_CNGCHMAP(ch_map); } rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); if (rc != 0) {
