The branch main has been updated by oh: URL: https://cgit.FreeBSD.org/src/commit/?id=9d56f84df5a60e012c79e694284de7d58ad0b029
commit 9d56f84df5a60e012c79e694284de7d58ad0b029 Author: Oskar Holmlund <[email protected]> AuthorDate: 2025-12-15 17:47:17 +0000 Commit: Oskar Holmlund <[email protected]> CommitDate: 2025-12-15 17:47:17 +0000 remove sys/dts/arm/socfpga_*_sdmmc.dts These two files are broken due to Linux 6.5 DTS import. Both of these boards have support in Linux DTS tree, please use these DTS instead. Removed and not fixed because of commit 949efdaa1db8 Approved by: br, manu (mentor) Differential revision: https://reviews.freebsd.org/D54216 --- sys/dts/arm/socfpga_arria10_socdk_sdmmc.dts | 118 -------------------------- sys/dts/arm/socfpga_cyclone5_sockit_sdmmc.dts | 72 ---------------- 2 files changed, 190 deletions(-) diff --git a/sys/dts/arm/socfpga_arria10_socdk_sdmmc.dts b/sys/dts/arm/socfpga_arria10_socdk_sdmmc.dts deleted file mode 100644 index b8ddf4dfafbc..000000000000 --- a/sys/dts/arm/socfpga_arria10_socdk_sdmmc.dts +++ /dev/null @@ -1,118 +0,0 @@ -/*- - * Copyright (c) 2017 Ruslan Bukin <[email protected]> - * All rights reserved. - * - * This software was developed by SRI International and the University of - * Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237 - * ("CTSRD"), as part of the DARPA CRASH research programme. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -/dts-v1/; -#include "socfpga_arria10_socdk.dtsi" - -/ { - model = "Altera SOCFPGA Arria 10"; - compatible = "altr,socfpga-arria10", "altr,socfpga"; - - /* Reserve first page for secondary CPU trampoline code */ - memreserve = < 0x00000000 0x1000 >; - - soc { - /* Local timer */ - timer@ffffc600 { - clock-frequency = <200000000>; - }; - - /* Global timer */ - global_timer: timer@ffffc200 { - compatible = "arm,cortex-a9-global-timer"; - reg = <0xffffc200 0x20>; - interrupts = <1 11 0x301>; - clock-frequency = <200000000>; - }; - }; - - chosen { - stdin = "serial1"; - stdout = "serial1"; - }; -}; - -&uart1 { - clock-frequency = < 50000000 >; -}; - -&mmc { - status = "okay"; - num-slots = <1>; - cap-sd-highspeed; - broken-cd; - bus-width = <4>; - bus-frequency = <200000000>; -}; - -&i2c1 { - lcd@28 { - compatible = "newhaven,nhd-0216k3z-nsw-bbw"; - reg = <0x28>; - }; -}; - -&usb0 { - dr_mode = "host"; -}; - -&qspi { - status = "okay"; - - dmas = <&pdma 24>, <&pdma 25>; - dma-names = "tx", "rx"; - - flash0: n25q00@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "n25q00aa"; - reg = <0>; - spi-max-frequency = <100000000>; - - m25p,fast-read; - cdns,page-size = <256>; - cdns,block-size = <16>; - cdns,read-delay = <4>; - cdns,tshsl-ns = <50>; - cdns,tsd2d-ns = <50>; - cdns,tchsh-ns = <4>; - cdns,tslch-ns = <4>; - - partition@qspi-boot { - label = "boot"; - reg = <0x0 0x2720000>; - }; - - partition@qspi-rootfs { - label = "rootfs"; - reg = <0x2720000 0x58E0000>; - }; - }; -}; diff --git a/sys/dts/arm/socfpga_cyclone5_sockit_sdmmc.dts b/sys/dts/arm/socfpga_cyclone5_sockit_sdmmc.dts deleted file mode 100644 index 4a08328847a4..000000000000 --- a/sys/dts/arm/socfpga_cyclone5_sockit_sdmmc.dts +++ /dev/null @@ -1,72 +0,0 @@ -/*- - * Copyright (c) 2017 Ruslan Bukin <[email protected]> - * All rights reserved. - * - * This software was developed by SRI International and the University of - * Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237 - * ("CTSRD"), as part of the DARPA CRASH research programme. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -/* /dts-v1/; */ -#include "socfpga_cyclone5_sockit.dts" - -/ { - model = "Terasic SoCkit"; - compatible = "altr,socfpga-cyclone5", "altr,socfpga"; - - /* Reserve first page for secondary CPU trampoline code */ - memreserve = < 0x00000000 0x1000 >; - - soc { - /* Local timer */ - timer@fffec600 { - clock-frequency = <200000000>; - }; - - /* Global timer */ - global_timer: timer@fffec200 { - compatible = "arm,cortex-a9-global-timer"; - reg = <0xfffec200 0x20>; - interrupts = <1 11 0xf04>; - clock-frequency = <200000000>; - }; - }; - - chosen { - stdin = "serial0"; - stdout = "serial0"; - }; -}; - -&mmc0 { - bus-frequency = <25000000>; -}; - -&uart0 { - clock-frequency = <100000000>; -}; - -&uart1 { - status = "disabled"; -};
