The branch main has been updated by imp: URL: https://cgit.FreeBSD.org/src/commit/?id=b55d106df9785d141f9e3e1c916e921df9d877ac
commit b55d106df9785d141f9e3e1c916e921df9d877ac Author: Martin Filla <[email protected]> AuthorDate: 2025-09-09 14:34:38 +0000 Commit: Warner Losh <[email protected]> CommitDate: 2026-01-10 05:05:38 +0000 ophgo: import new .dts Signed-off-by: Martin Filla <[email protected]> Reviewed by: imp Pull Request: https://github.com/freebsd/freebsd-src/pull/1844 --- .../include/dt-bindings/clock/cv181x-clock.h | 175 ++++ .../include/dt-bindings/dma/cv181x-dmamap.h | 48 ++ .../include/dt-bindings/reset/cv181x-resets.h | 172 ++++ .../src/riscv/sophgo/cv181x_asic_bga.dtsi | 56 ++ .../src/riscv/sophgo/cv181x_asic_emmc.dtsi | 4 + .../src/riscv/sophgo/cv181x_asic_qfn.dtsi | 120 +++ .../src/riscv/sophgo/cv181x_asic_sd.dtsi | 4 + .../src/riscv/sophgo/cv181x_asic_spinand.dtsi | 5 + .../src/riscv/sophgo/cv181x_asic_spinor.dtsi | 5 + .../device-tree/src/riscv/sophgo/cv181x_base.dtsi | 932 +++++++++++++++++++++ .../src/riscv/sophgo/cv181x_base_arm.dtsi | 320 +++++++ .../src/riscv/sophgo/cv181x_base_riscv.dtsi | 378 +++++++++ .../src/riscv/sophgo/cv181x_default_memmap.dtsi | 25 + .../sophgo/sg2000_milkv_duos_glibc_arm64_emmc.dts | 108 +++ .../sophgo/sg2000_milkv_duos_glibc_arm64_sd.dts | 112 +++ .../sophgo/sg2000_milkv_duos_musl_riscv64_emmc.dts | 108 +++ .../sophgo/sg2000_milkv_duos_musl_riscv64_sd.dts | 108 +++ .../src/riscv/sophgo/sg2000_wevb_arm64_sd.dts | 13 + .../src/riscv/sophgo/sg2000_wevb_riscv64_sd.dts | 10 + sys/modules/dtb/sophgo/Makefile | 15 + sys/riscv/conf/GENERIC | 1 + sys/riscv/conf/std.sophgo | 8 + sys/riscv/sophgo/files.sophgo | 2 + 23 files changed, 2729 insertions(+) diff --git a/sys/contrib/device-tree/include/dt-bindings/clock/cv181x-clock.h b/sys/contrib/device-tree/include/dt-bindings/clock/cv181x-clock.h new file mode 100644 index 000000000000..ed76e4d8ef95 --- /dev/null +++ b/sys/contrib/device-tree/include/dt-bindings/clock/cv181x-clock.h @@ -0,0 +1,175 @@ +/* + * Copyright (C) Cvitek Co., Ltd. 2019-2021. All rights reserved. + * + * File Name: cv181x-clock.h + * Description: + */ + +#ifndef __DT_BINDINGS_CLK_CV181X_H__ +#define __DT_BINDINGS_CLK_CV181X_H__ + +#define CV181X_CLK_MPLL 0 +#define CV181X_CLK_TPLL 1 +#define CV181X_CLK_FPLL 2 +#define CV181X_CLK_MIPIMPLL 3 +#define CV181X_CLK_A0PLL 4 +#define CV181X_CLK_DISPPLL 5 +#define CV181X_CLK_CAM0PLL 6 +#define CV181X_CLK_CAM1PLL 7 + +#define CV181X_CLK_MIPIMPLL_D3 8 +#define CV181X_CLK_CAM0PLL_D2 9 +#define CV181X_CLK_CAM0PLL_D3 10 + +#define CV181X_CLK_A53 11 +#define CV181X_CLK_CPU_AXI0 12 +#define CV181X_CLK_CPU_GIC 13 +#define CV181X_CLK_XTAL_A53 14 +#define CV181X_CLK_TPU 15 +#define CV181X_CLK_TPU_FAB 16 +#define CV181X_CLK_AHB_ROM 17 +#define CV181X_CLK_DDR_AXI_REG 18 +#define CV181X_CLK_RTC_25M 19 +#define CV181X_CLK_TEMPSEN 20 +#define CV181X_CLK_SARADC 21 +#define CV181X_CLK_EFUSE 22 +#define CV181X_CLK_APB_EFUSE 23 +#define CV181X_CLK_DEBUG 24 +#define CV181X_CLK_XTAL_MISC 25 +#define CV181X_CLK_AXI4_EMMC 26 +#define CV181X_CLK_EMMC 27 +#define CV181X_CLK_100K_EMMC 28 +#define CV181X_CLK_AXI4_SD0 29 +#define CV181X_CLK_SD0 30 +#define CV181X_CLK_100K_SD0 31 +#define CV181X_CLK_AXI4_SD1 32 +#define CV181X_CLK_SD1 33 +#define CV181X_CLK_100K_SD1 34 +#define CV181X_CLK_SPI_NAND 35 +#define CV181X_CLK_500M_ETH0 36 +#define CV181X_CLK_AXI4_ETH0 37 +#define CV181X_CLK_500M_ETH1 38 +#define CV181X_CLK_AXI4_ETH1 39 +#define CV181X_CLK_APB_GPIO 40 +#define CV181X_CLK_APB_GPIO_INTR 41 +#define CV181X_CLK_GPIO_DB 42 +#define CV181X_CLK_AHB_SF 43 +#define CV181X_CLK_SDMA_AXI 44 +#define CV181X_CLK_SDMA_AUD0 45 +#define CV181X_CLK_SDMA_AUD1 46 +#define CV181X_CLK_SDMA_AUD2 47 +#define CV181X_CLK_SDMA_AUD3 48 +#define CV181X_CLK_APB_I2C 49 +#define CV181X_CLK_APB_WDT 50 +#define CV181X_CLK_PWM 51 +#define CV181X_CLK_APB_SPI0 52 +#define CV181X_CLK_APB_SPI1 53 +#define CV181X_CLK_APB_SPI2 54 +#define CV181X_CLK_APB_SPI3 55 +#define CV181X_CLK_CAM0_200 56 +#define CV181X_CLK_UART0 57 +#define CV181X_CLK_APB_UART0 58 +#define CV181X_CLK_UART1 59 +#define CV181X_CLK_APB_UART1 60 +#define CV181X_CLK_UART2 61 +#define CV181X_CLK_APB_UART2 62 +#define CV181X_CLK_UART3 63 +#define CV181X_CLK_APB_UART3 64 +#define CV181X_CLK_UART4 65 +#define CV181X_CLK_APB_UART4 66 +#define CV181X_CLK_APB_I2S0 67 +#define CV181X_CLK_APB_I2S1 68 +#define CV181X_CLK_APB_I2S2 69 +#define CV181X_CLK_APB_I2S3 70 +#define CV181X_CLK_AXI4_USB 71 +#define CV181X_CLK_APB_USB 72 +#define CV181X_CLK_125M_USB 73 +#define CV181X_CLK_33K_USB 74 +#define CV181X_CLK_12M_USB 75 +#define CV181X_CLK_AXI4 76 +#define CV181X_CLK_AXI6 77 +#define CV181X_CLK_DSI_ESC 78 +#define CV181X_CLK_AXI_VIP 79 +#define CV181X_CLK_SRC_VIP_SYS_0 80 +#define CV181X_CLK_SRC_VIP_SYS_1 81 +#define CV181X_CLK_DISP_SRC_VIP 82 +#define CV181X_CLK_AXI_VIDEO_CODEC 83 +#define CV181X_CLK_VC_SRC0 84 +#define CV181X_CLK_H264C 85 +#define CV181X_CLK_H265C 86 +#define CV181X_CLK_JPEG 87 +#define CV181X_CLK_APB_JPEG 88 +#define CV181X_CLK_APB_H264C 89 +#define CV181X_CLK_APB_H265C 90 +#define CV181X_CLK_CAM0 91 +#define CV181X_CLK_CAM1 92 +#define CV181X_CLK_CSI_MAC0_VIP 93 +#define CV181X_CLK_CSI_MAC1_VIP 94 +#define CV181X_CLK_ISP_TOP_VIP 95 +#define CV181X_CLK_IMG_D_VIP 96 +#define CV181X_CLK_IMG_V_VIP 97 +#define CV181X_CLK_SC_TOP_VIP 98 +#define CV181X_CLK_SC_D_VIP 99 +#define CV181X_CLK_SC_V1_VIP 100 +#define CV181X_CLK_SC_V2_VIP 101 +#define CV181X_CLK_SC_V3_VIP 102 +#define CV181X_CLK_DWA_VIP 103 +#define CV181X_CLK_BT_VIP 104 +#define CV181X_CLK_DISP_VIP 105 +#define CV181X_CLK_DSI_MAC_VIP 106 +#define CV181X_CLK_LVDS0_VIP 107 +#define CV181X_CLK_LVDS1_VIP 108 +#define CV181X_CLK_CSI0_RX_VIP 109 +#define CV181X_CLK_CSI1_RX_VIP 110 +#define CV181X_CLK_PAD_VI_VIP 111 +#define CV181X_CLK_1M 112 +#define CV181X_CLK_SPI 113 +#define CV181X_CLK_I2C 114 +#define CV181X_CLK_PM 115 +#define CV181X_CLK_TIMER0 116 +#define CV181X_CLK_TIMER1 117 +#define CV181X_CLK_TIMER2 118 +#define CV181X_CLK_TIMER3 119 +#define CV181X_CLK_TIMER4 120 +#define CV181X_CLK_TIMER5 121 +#define CV181X_CLK_TIMER6 122 +#define CV181X_CLK_TIMER7 123 +#define CV181X_CLK_APB_I2C0 124 +#define CV181X_CLK_APB_I2C1 125 +#define CV181X_CLK_APB_I2C2 126 +#define CV181X_CLK_APB_I2C3 127 +#define CV181X_CLK_APB_I2C4 128 +#define CV181X_CLK_WGN 129 +#define CV181X_CLK_WGN0 130 +#define CV181X_CLK_WGN1 131 +#define CV181X_CLK_WGN2 132 +#define CV181X_CLK_KEYSCAN 133 +#define CV181X_CLK_AHB_SF1 134 +#define CV181X_CLK_VC_SRC1 135 +#define CV181X_CLK_SRC_VIP_SYS_2 136 +#define CV181X_CLK_PAD_VI1_VIP 137 +#define CV181X_CLK_CFG_REG_VIP 138 +#define CV181X_CLK_CFG_REG_VC 139 +#define CV181X_CLK_AUDSRC 140 +#define CV181X_CLK_APB_AUDSRC 141 +#define CV181X_CLK_VC_SRC2 142 +#define CV181X_CLK_PWM_SRC 143 +#define CV181X_CLK_AP_DEBUG 144 +#define CV181X_CLK_SRC_RTC_SYS_0 145 +#define CV181X_CLK_PAD_VI2_VIP 146 +#define CV181X_CLK_CSI_BE_VIP 147 +#define CV181X_CLK_VIP_IP0 148 +#define CV181X_CLK_VIP_IP1 149 +#define CV181X_CLK_VIP_IP2 150 +#define CV181X_CLK_VIP_IP3 151 +#define CV181X_CLK_C906_0 152 +#define CV181X_CLK_C906_1 153 +#define CV181X_CLK_SRC_VIP_SYS_3 154 +#define CV181X_CLK_SRC_VIP_SYS_4 155 +#define CV181X_CLK_IVE_VIP 156 +#define CV181X_CLK_RAW_VIP 157 +#define CV181X_CLK_OSDC_VIP 158 +#define CV181X_CLK_CSI_MAC2_VIP 159 +#define CV181X_CLK_CAM0_VIP 160 + +#endif /* __DT_BINDINGS_CLK_CV181X_H__ */ diff --git a/sys/contrib/device-tree/include/dt-bindings/dma/cv181x-dmamap.h b/sys/contrib/device-tree/include/dt-bindings/dma/cv181x-dmamap.h new file mode 100644 index 000000000000..84a4c3664ee1 --- /dev/null +++ b/sys/contrib/device-tree/include/dt-bindings/dma/cv181x-dmamap.h @@ -0,0 +1,48 @@ +#ifndef __DT_BINDINGS_CV181X_DMAMAP_H__ +#define __DT_BINDINGS_CV181X_DMAMAP_H__ + +#define CVI_I2S0_RX 0 +#define CVI_I2S0_TX 1 +#define CVI_I2S1_RX 2 +#define CVI_I2S1_TX 3 +#define CVI_I2S2_RX 4 +#define CVI_I2S2_TX 5 +#define CVI_I2S3_RX 6 +#define CVI_I2S3_TX 7 +#define CVI_UART0_RX 8 +#define CVI_UART0_TX 9 +#define CVI_UART1_RX 10 +#define CVI_UART1_TX 11 +#define CVI_UART2_RX 12 +#define CVI_UART2_TX 13 +#define CVI_UART3_RX 14 +#define CVI_UART3_TX 15 +#define CVI_SPI0_RX 16 +#define CVI_SPI0_TX 17 +#define CVI_SPI1_RX 18 +#define CVI_SPI1_TX 19 +#define CVI_SPI2_RX 20 +#define CVI_SPI2_TX 21 +#define CVI_SPI3_RX 22 +#define CVI_SPI3_TX 23 +#define CVI_I2C0_RX 24 +#define CVI_I2C0_TX 25 +#define CVI_I2C1_RX 26 +#define CVI_I2C1_TX 27 +#define CVI_I2C2_RX 28 +#define CVI_I2C2_TX 29 +#define CVI_I2C3_RX 30 +#define CVI_I2C3_TX 31 +#define CVI_I2C4_RX 32 +#define CVI_I2C4_TX 33 +#define CVI_TDM0_RX 34 +#define CVI_TDM0_TX 35 +#define CVI_TDM1_RX 36 +#define CVI_AUDSRC 37 +#define CVI_SPI_NAND 38 +#define CVI_SPI_NOR 39 +#define CVI_UART4_RX 40 +#define CVI_UART4_TX 41 +#define CVI_SPI_NOR1 42 + +#endif diff --git a/sys/contrib/device-tree/include/dt-bindings/reset/cv181x-resets.h b/sys/contrib/device-tree/include/dt-bindings/reset/cv181x-resets.h new file mode 100644 index 000000000000..e10d33b35446 --- /dev/null +++ b/sys/contrib/device-tree/include/dt-bindings/reset/cv181x-resets.h @@ -0,0 +1,172 @@ +/* + * Copyright (C) Cvitek Co., Ltd. 2019-2020. All rights reserved. + * + * File Name: cvi_template.h + * Description: + */ + +#ifndef __DT_BINDINGS_RST_CV181X_H__ +#define __DT_BINDINGS_RST_CV181X_H__ + +#define RST_MAINRST_AP 0 +#define RST_SECONDRST_AP 1 +#define RST_DDR 2 +#define RST_H264C 3 +#define RST_JPEG 4 +#define RST_H265C 5 +#define RST_VIPSYS 6 +#define RST_TDMA 7 +#define RST_TPU 8 +#define RST_TPUSYS 9 +#define RST_TSM 10 +#define RST_USB 11 +#define RST_ETH0 12 +#define RST_ETH1 13 +#define RST_NAND 14 +#define RST_EMMC 15 +#define RST_SD0 16 +#define RST_SD1 17 +#define RST_SDMA 18 +#define RST_I2S0 19 +#define RST_I2S1 20 +#define RST_I2S2 21 +#define RST_I2S3 22 +#define RST_UART0 23 +#define RST_UART1 24 +#define RST_UART2 25 +#define RST_UART3 26 +#define RST_I2C0 27 +#define RST_I2C1 28 +#define RST_I2C2 29 +#define RST_I2C3 30 +#define RST_I2C4 31 +#define RST_PWM0 32 +#define RST_PWM1 33 +#define RST_PWM2 34 +#define RST_PWM3 35 +#define RST_PWM4 36 +#define RST_PWM5 37 +#define RST_PWM6 38 +#define RST_PWM7 39 +#define RST_SPI0 40 +#define RST_SPI1 41 +#define RST_SPI2 42 +#define RST_SPI3 43 +#define RST_GPIO0 44 +#define RST_GPIO1 45 +#define RST_GPIO2 46 +#define RST_EFUSE 47 +#define RST_WDT 48 +#define RST_AHBRST_ROM 49 +#define RST_SPIC 50 +#define RST_TEMPSEN 51 +#define RST_SARADC 52 +#define RST_PCIERST_CDMA 53 +#define RST_PCIERST_SMMU 54 +#define RST_PCIERST_PCIE 55 +#define RST_PCIERST_FABS 56 +#define RST_PCIERST_IRQ 57 +#define RST_COMBORST_PHY0 58 +#define RST_COMBORST_PHY1 59 +#define RST_USB1 60 +#define RST_SPIRST_NAND 61 +#define RST_SE 62 +#define RST_RTCRST_SWRST_ONLY 63 +#define RST_CPUCORE0 64 +#define RST_CPUCORE1 65 +#define RST_CPUCORE2 66 +#define RST_CPUCORE3 67 +#define RST_DSIPHY 68 +#define RST_DSIPHYRST_APB 69 +#define RST_CSIPHY0 70 +#define RST_CSIPHY0RST_APB 71 +#define RST_CSIPHY1 72 +#define RST_CSIPHY1RST_APB 73 +#define RST_UART4 74 +#define RST_GPIO3 75 +#define RST_SYSTEM 76 +#define RST_TIMER 77 +#define RST_TIMER0 78 +#define RST_TIMER1 79 +#define RST_TIMER2 80 +#define RST_TIMER3 81 +#define RST_TIMER4 82 +#define RST_TIMER5 83 +#define RST_TIMER6 84 +#define RST_TIMER7 85 +#define RST_WGN0 86 +#define RST_WGN1 87 +#define RST_WGN2 88 +#define RST_KEYSCAN 89 +#define RST_SPIC1 90 +#define RST_AUDDAC 91 +#define RST_AUDDACRST_APB 92 +#define RST_AUDADC 93 +#define RST_AUDADCRST_APB 94 +#define RST_VCSYS 95 +#define RST_ETHPHY 96 +#define RST_ETHPHYRST_APB 97 +#define RST_AUDSRC 98 +#define RST_AUTO_CLEAR_CPUCORE0 99 +#define RST_AUTO_CLEAR_CPUCORE1 100 +#define RST_AUTO_CLEAR_CPUCORE2 101 +#define RST_AUTO_CLEAR_CPUCORE3 102 +#define RST_AUTO_CLEAR_MAINRST_AP 103 +#define RST_AUTO_CLEAR_SECONDRST_AP 104 + +#define CLK_RST_A53 0 +#define CLK_RST_50M_A53 1 +#define CLK_RST_AHB_ROM 2 +#define CLK_RST_AXI_SRAM 3 +#define CLK_RST_DDR_AXI 4 +#define CLK_RST_EFUSE 5 +#define CLK_RST_APB_EFUSE 6 +#define CLK_RST_AXI_EMMC 7 +#define CLK_RST_EMMC 8 +#define CLK_RST_100K_EMMC 9 +#define CLK_RST_AXI_SD 10 +#define CLK_RST_SD 11 +#define CLK_RST_100K_SD 12 +#define CLK_RST_500M_ETH0 13 +#define CLK_RST_AXI_ETH0 14 +#define CLK_RST_500M_ETH1 15 +#define CLK_RST_AXI_ETH1 16 +#define CLK_RST_AXI_GDMA 17 +#define CLK_RST_APB_GPIO 18 +#define CLK_RST_APB_GPIO_INTR 19 +#define CLK_RST_GPIO_DB 20 +#define CLK_RST_AXI_MINER 21 +#define CLK_RST_AHB_SF 22 +#define CLK_RST_SDMA_AXI 23 +#define CLK_RST_SDMA_AUD 24 +#define CLK_RST_APB_I2C 25 +#define CLK_RST_APB_WDT 26 +#define CLK_RST_APB_JPEG 27 +#define CLK_RST_JPEG_AXI 28 +#define CLK_RST_AXI_NF 29 +#define CLK_RST_APB_NF 30 +#define CLK_RST_NF 31 +#define CLK_RST_APB_PWM 32 +#define CLK_RST_RV 33 +#define CLK_RST_APB_SPI 34 +#define CLK_RST_TPU_AXI 35 +#define CLK_RST_UART_500M 36 +#define CLK_RST_APB_UART 37 +#define CLK_RST_APB_I2S 38 +#define CLK_RST_AXI_USB 39 +#define CLK_RST_APB_USB 40 +#define CLK_RST_125M_USB 41 +#define CLK_RST_33K_USB 42 +#define CLK_RST_12M_USB 43 +#define CLK_RST_APB_VIDEO 44 +#define CLK_RST_VIDEO_AXI 45 +#define CLK_RST_VPP_AXI 46 +#define CLK_RST_APB_VPP 47 +#define CLK_RST_AXI1 48 +#define CLK_RST_AXI2 49 +#define CLK_RST_AXI3 50 +#define CLK_RST_AXI4 51 +#define CLK_RST_AXI5 52 +#define CLK_RST_AXI6 53 + +#endif /* _DT_BINDINGS_RST_CV1835_H_ */ diff --git a/sys/contrib/device-tree/src/riscv/sophgo/cv181x_asic_bga.dtsi b/sys/contrib/device-tree/src/riscv/sophgo/cv181x_asic_bga.dtsi new file mode 100644 index 000000000000..93039e182782 --- /dev/null +++ b/sys/contrib/device-tree/src/riscv/sophgo/cv181x_asic_bga.dtsi @@ -0,0 +1,56 @@ +&dac{ + mute-gpio-l = <&porta 15 GPIO_ACTIVE_LOW>; + mute-gpio-r = <&porta 30 GPIO_ACTIVE_LOW>; +}; + +&spi0 { + status = "disabled"; + num-cs = <1>; + spidev@0 { + compatible = "rohm,dh2228fv"; + spi-max-frequency = <1000000>; + reg = <0>; + }; +}; + +&spi1 { + status = "disabled"; + num-cs = <1>; + spidev@0 { + compatible = "rohm,dh2228fv"; + spi-max-frequency = <1000000>; + reg = <0>; + }; +}; + +&spi2 { + status = "disabled"; + num-cs = <1>; + spidev@0 { + compatible = "rohm,dh2228fv"; + spi-max-frequency = <1000000>; + reg = <0>; + }; +}; + +&spi3 { + status = "okay"; + num-cs = <1>; + spidev@0 { + compatible = "rohm,dh2228fv"; + spi-max-frequency = <1000000>; + reg = <0>; + }; +}; + +&i2c1 { + status = "disabled"; +}; + +/ { + /delete-node/ i2s@04110000; + /delete-node/ i2s@04120000; + /delete-node/ sound_ext1; + /delete-node/ sound_ext2; + /delete-node/ sound_PDM; +}; diff --git a/sys/contrib/device-tree/src/riscv/sophgo/cv181x_asic_emmc.dtsi b/sys/contrib/device-tree/src/riscv/sophgo/cv181x_asic_emmc.dtsi new file mode 100644 index 000000000000..507a3a46b342 --- /dev/null +++ b/sys/contrib/device-tree/src/riscv/sophgo/cv181x_asic_emmc.dtsi @@ -0,0 +1,4 @@ +/ { + /delete-node/ cvi-spif@10000000; + /delete-node/ cv-spinf@4060000; +}; diff --git a/sys/contrib/device-tree/src/riscv/sophgo/cv181x_asic_qfn.dtsi b/sys/contrib/device-tree/src/riscv/sophgo/cv181x_asic_qfn.dtsi new file mode 100644 index 000000000000..5d81e8c2cedc --- /dev/null +++ b/sys/contrib/device-tree/src/riscv/sophgo/cv181x_asic_qfn.dtsi @@ -0,0 +1,120 @@ +&sd { + no-1-8-v; +}; + +&mipi_rx{ + snsr-reset = <&portc 13 GPIO_ACTIVE_LOW>, <&portc 13 GPIO_ACTIVE_LOW>, <&portc 13 GPIO_ACTIVE_LOW>; +}; + +&mipi_tx { + reset-gpio = <&porta 15 GPIO_ACTIVE_LOW>; + pwm-gpio = <&porta 18 GPIO_ACTIVE_HIGH>; + power-ct-gpio = <&porta 19 GPIO_ACTIVE_HIGH>; +}; + +&dac{ + mute-gpio-r = <&porte 2 GPIO_ACTIVE_LOW>; +}; + +&spi0 { + status = "disabled"; + num-cs = <1>; + spidev@0 { + compatible = "rohm,dh2228fv"; + spi-max-frequency = <1000000>; + reg = <0>; + }; +}; + +&spi1 { + status = "disabled"; + num-cs = <1>; + spidev@0 { + compatible = "rohm,dh2228fv"; + spi-max-frequency = <1000000>; + reg = <0>; + }; +}; + +&spi2 { + status = "disabled"; + num-cs = <1>; + spidev@0 { + compatible = "rohm,dh2228fv"; + spi-max-frequency = <1000000>; + reg = <0>; + }; +}; + +&spi3 { + status = "okay"; + num-cs = <1>; + spidev@0 { + compatible = "rohm,dh2228fv"; + spi-max-frequency = <1000000>; + reg = <0>; + }; +}; + +#ifndef CONFIG_PM +&i2c0 { + /* FMUX_GPIO_REG iic_func_sel gpio_func_sel */ + scl-pinmux = <0x03001070 0x0 0x3>; // IIC0_SCL/IIC0_SCL/XGPIOA[28] + sda-pinmux = <0x03001074 0x0 0x3>; // IIC0_SDA/IIC0_SDA/XGPIOA[29] + /* gpio port */ + scl-gpios = <&porta 28 GPIO_ACTIVE_HIGH>; + sda-gpios = <&porta 29 GPIO_ACTIVE_HIGH>; +}; + +&i2c1 { + /* FMUX_GPIO_REG iic_func_sel gpio_func_sel */ + scl-pinmux = <0x03009408 0x2 0x3>; // SPI1_MOSI/IIC1_SCL/XGPIOB[7] + sda-pinmux = <0x0300940c 0x2 0x3>; // SPI1_MISO/IIC1_SDA/XGPIOB[8] + /* gpio port */ + scl-gpios = <&portb 7 GPIO_ACTIVE_HIGH>; + sda-gpios = <&portb 8 GPIO_ACTIVE_HIGH>; +}; + +&i2c2 { + /* FMUX_GPIO_REG iic_func_sel gpio_func_sel */ + scl-pinmux = <0x030011a0 0x4 0x3>; // PAD_MIPI_TXP1/IIC2_SCL/XGPIOC[15] + sda-pinmux = <0x0300119c 0x4 0x3>; // PAD_MIPI_TXM1/IIC2_SDA/XGPIOC[14] + /* gpio port */ + scl-gpios = <&portc 15 GPIO_ACTIVE_HIGH>; + sda-gpios = <&portc 14 GPIO_ACTIVE_HIGH>; +}; + +&i2c3 { + /* FMUX_GPIO_REG iic_func_sel gpio_func_sel */ + scl-pinmux = <0x03001014 0x0 0x3>; // IIC3_SCL/IIC3_SCL/XGPIOA[5] + sda-pinmux = <0x03001018 0x0 0x3>; // IIC3_SDA/IIC3_SDA/XGPIOA[6] + /* gpio port */ + scl-gpios = <&porta 5 GPIO_ACTIVE_HIGH>; + sda-gpios = <&porta 6 GPIO_ACTIVE_HIGH>; +}; + +&i2c4 { + /* FMUX_GPIO_REG iic_func_sel gpio_func_sel */ + scl-pinmux = <0x030010f0 0x2 0x3>; // ADC3/IIC4_SCL/XGPIOB[1] + sda-pinmux = <0x030010f4 0x2 0x3>; // ADC2/IIC4_SDA/XGPIOB[2] + /* gpio port */ + scl-gpios = <&portb 1 GPIO_ACTIVE_HIGH>; + sda-gpios = <&portb 2 GPIO_ACTIVE_HIGH>; +}; +#endif + +/ { + /delete-node/ wifi-sd@4320000; + /delete-node/ i2s@04110000; + /delete-node/ i2s@04120000; + /delete-node/ sound_ext1; + /delete-node/ sound_ext2; + /delete-node/ sound_PDM; + + wifi_pin { + compatible = "cvitek,wifi-pin"; + poweron-gpio = <&porte 2 GPIO_ACTIVE_HIGH>; + wakeup-gpio = <&porte 6 GPIO_ACTIVE_HIGH>; + }; + +}; diff --git a/sys/contrib/device-tree/src/riscv/sophgo/cv181x_asic_sd.dtsi b/sys/contrib/device-tree/src/riscv/sophgo/cv181x_asic_sd.dtsi new file mode 100644 index 000000000000..5af9620d8630 --- /dev/null +++ b/sys/contrib/device-tree/src/riscv/sophgo/cv181x_asic_sd.dtsi @@ -0,0 +1,4 @@ +/ { + /delete-node/ cv-emmc@4300000; + /delete-node/ cv-spinf@4060000; +}; diff --git a/sys/contrib/device-tree/src/riscv/sophgo/cv181x_asic_spinand.dtsi b/sys/contrib/device-tree/src/riscv/sophgo/cv181x_asic_spinand.dtsi new file mode 100644 index 000000000000..2c3c6065caa3 --- /dev/null +++ b/sys/contrib/device-tree/src/riscv/sophgo/cv181x_asic_spinand.dtsi @@ -0,0 +1,5 @@ +/ { + /delete-node/ cvi-spif@10000000; + /delete-node/ cv-emmc@4300000; +}; + diff --git a/sys/contrib/device-tree/src/riscv/sophgo/cv181x_asic_spinor.dtsi b/sys/contrib/device-tree/src/riscv/sophgo/cv181x_asic_spinor.dtsi new file mode 100644 index 000000000000..cd125408284a --- /dev/null +++ b/sys/contrib/device-tree/src/riscv/sophgo/cv181x_asic_spinor.dtsi @@ -0,0 +1,5 @@ +/ { + /delete-node/ cv-emmc@4300000; + /delete-node/ cv-spinf@4060000; +}; + diff --git a/sys/contrib/device-tree/src/riscv/sophgo/cv181x_base.dtsi b/sys/contrib/device-tree/src/riscv/sophgo/cv181x_base.dtsi new file mode 100644 index 000000000000..13747090dfa6 --- /dev/null +++ b/sys/contrib/device-tree/src/riscv/sophgo/cv181x_base.dtsi @@ -0,0 +1,932 @@ + +/ { + compatible = "cvitek,cv181x"; + + #size-cells = <0x2>; + #address-cells = <0x2>; + + top_misc:top_misc_ctrl@3000000 { + compatible = "syscon"; + reg = <0x0 0x03000000 0x0 0x8000>; + }; + + clk_rst: clk-reset-controller { + #reset-cells = <1>; + compatible = "cvitek,clk-reset"; + reg = <0x0 0x03002000 0x0 0x8>; + }; + + osc: oscillator { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <25000000>; + clock-output-names = "osc"; + }; + + clk: clock-controller { + compatible = "cvitek,cv181x-clk"; + reg = <0x0 0x03002000 0x0 0x1000>; + clocks = <&osc>; + #clock-cells = <1>; + }; + + rst: reset-controller { + #reset-cells = <1>; + compatible = "cvitek,reset"; + reg = <0x0 0x03003000 0x0 0x10>; + }; + + restart: restart-controller { + compatible = "cvitek,restart"; + reg = <0x0 0x05025000 0x0 0x2000>; + }; + + tpu { + compatible = "cvitek,tpu"; + reg-names = "tdma", "tiu"; + reg = <0x0 0x0C100000 0x0 0x1000>, + <0x0 0x0C101000 0x0 0x1000>; + clocks = <&clk CV181X_CLK_TPU>, <&clk CV181X_CLK_TPU_FAB>; + clock-names = "clk_tpu_axi", "clk_tpu_fab"; + resets = <&rst RST_TDMA>, <&rst RST_TPU>, <&rst RST_TPUSYS>; + reset-names = "res_tdma", "res_tpu", "res_tpusys"; + }; + + mon { + compatible = "cvitek,mon"; + reg-names = "pcmon", "ddr_ctrl", "ddr_phyd", "ddr_aximon", "ddr_top"; + reg = <0x0 0x01040000 0x0 0x1000>, + <0x0 0x08004000 0x0 0x1000>, + <0x0 0x08006000 0x0 0x1000>, + <0x0 0x08008000 0x0 0x1000>, + <0x0 0x0800A000 0x0 0x1000>; + }; + + wiegand0 { + compatible = "cvitek,wiegand"; + reg-names = "wiegand"; + reg = <0x0 0x03030000 0x0 0x1000>; + clocks = <&clk CV181X_CLK_WGN>, <&clk CV181X_CLK_WGN0>; + clock-names = "clk_wgn", "clk_wgn1"; + resets = <&rst RST_WGN0>; + reset-names = "res_wgn"; + }; + + wiegand1 { + compatible = "cvitek,wiegand"; + reg-names = "wiegand"; + reg = <0x0 0x03031000 0x0 0x1000>; + clocks = <&clk CV181X_CLK_WGN>, <&clk CV181X_CLK_WGN1>; + clock-names = "clk_wgn", "clk_wgn1"; + resets = <&rst RST_WGN1>; + reset-names = "res_wgn"; + }; + + wiegand2 { + compatible = "cvitek,wiegand"; + reg-names = "wiegand"; + reg = <0x0 0x03032000 0x0 0x1000>; + clocks = <&clk CV181X_CLK_WGN>, <&clk CV181X_CLK_WGN2>; + clock-names = "clk_wgn", "clk_wgn1"; + resets = <&rst RST_WGN2>; + reset-names = "res_wgn"; + }; + + saradc { + compatible = "cvitek,saradc"; + reg-names = "top_domain_saradc", "rtc_domain_saradc"; + reg = <0x0 0x030F0000 0x0 0x1000>, <0x0 0x0502c000 0x0 0x1000>; + clocks = <&clk CV181X_CLK_SARADC>; + clock-names = "clk_saradc"; + resets = <&rst RST_SARADC>; + reset-names = "res_saradc"; + }; + + rtc { + compatible = "cvitek,rtc"; + reg = <0x0 0x05026000 0x0 0x1000>,<0x0 0x05025000 0x0 0x1000>; + clocks = <&clk CV181X_CLK_RTC_25M>; + clock-names = "clk_rtc"; + }; + + cvitek-ion { + compatible = "cvitek,cvitek-ion"; + + heap_carveout@0 { + compatible = "cvitek,carveout"; + memory-region = <&ion_reserved>; + }; + }; + + sysdma_remap { + compatible = "cvitek,sysdma_remap"; + reg = <0x0 0x03000154 0x0 0x10>; + ch-remap = <CVI_I2S0_RX CVI_I2S2_TX CVI_I2S1_RX CVI_I2S1_TX + CVI_SPI_NAND CVI_SPI_NAND CVI_I2S2_RX CVI_I2S3_TX>; + int_mux_base = <0x03000298>; + }; + + dmac: dma@0x4330000 { + compatible = "snps,dmac-bm"; + reg = <0x0 0x04330000 0x0 0x1000>; + clock-names = "clk_sdma_axi"; + clocks = <&clk CV181X_CLK_SDMA_AXI>; + + dma-channels = /bits/ 8 <8>; + #dma-cells = <3>; + dma-requests = /bits/ 8 <16>; + chan_allocation_order = /bits/ 8 <0>; + chan_priority = /bits/ 8 <1>; + block_size = <1024>; + dma-masters = /bits/ 8 <2>; + data-width = <4 4>; /* bytes */ + axi_tr_width = <4>; /* bytes */ + block-ts = <15>; + }; + + + watchdog0: cv-wd@0x3010000 { + compatible = "snps,dw-wdt"; + reg = <0x0 0x03010000 0x0 0x1000>; + resets = <&rst RST_WDT>; + clocks = <&pclk>; + }; + + pwm0: pwm@3060000 { + compatible = "cvitek,cvi-pwm"; + reg = <0x0 0x3060000 0x0 0x1000>; + clocks = <&clk CV181X_CLK_PWM>; + #pwm-cells = <1>; + }; + + pwm1: pwm@3061000 { + compatible = "cvitek,cvi-pwm"; + reg = <0x0 0x3061000 0x0 0x1000>; + clocks = <&clk CV181X_CLK_PWM>; + #pwm-cells = <2>; + }; + + pwm2: pwm@3062000 { + compatible = "cvitek,cvi-pwm"; + reg = <0x0 0x3062000 0x0 0x1000>; + clocks = <&clk CV181X_CLK_PWM>; + #pwm-cells = <3>; + }; + + pwm3: pwm@3063000 { + compatible = "cvitek,cvi-pwm"; + reg = <0x0 0x3063000 0x0 0x1000>; + clocks = <&clk CV181X_CLK_PWM>; + #pwm-cells = <4>; + }; + + pclk: pclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <25000000>; + }; + + spinand:cv-spinf@4060000 { + compatible = "cvitek,cv1835-spinf"; + reg = <0x0 0x4060000 0x0 0x1000>; + reg-names = "core_mem"; + bus-width = <4>; + dmas = <&dmac 4 1 1 + &dmac 5 1 1>; + dma-names = "rx","tx"; + }; + + spif:cvi-spif@10000000 { + compatible = "cvitek,cvi-spif"; + bus-num = <0>; + reg = <0x0 0x10000000 0x0 0x10000000>; + reg-names = "spif"; + sck-div = <3>; + sck_mhz = <300>; + spi-max-frequency = <75000000>; + spiflash { + compatible = "jedec,spi-nor"; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + }; + }; + + spi0:spi0@04180000 { + compatible = "snps,dw-apb-ssi"; + reg = <0x0 0x04180000 0x0 0x10000>; + clocks = <&clk CV181X_CLK_SPI>; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi1:spi1@04190000 { + compatible = "snps,dw-apb-ssi"; + reg = <0x0 0x04190000 0x0 0x10000>; + clocks = <&clk CV181X_CLK_SPI>; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi2:spi2@041A0000 { + compatible = "snps,dw-apb-ssi"; + reg = <0x0 0x041A0000 0x0 0x10000>; + clocks = <&clk CV181X_CLK_SPI>; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi3:spi3@041B0000 { + compatible = "snps,dw-apb-ssi"; + reg = <0x0 0x041B0000 0x0 0x10000>; + clocks = <&clk CV181X_CLK_SPI>; + #address-cells = <1>; + #size-cells = <0>; +#if 0 + dmas = <&dmac 2 1 1 + &dmac 3 1 1>; + dma-names = "rx", "tx"; + capability = "txrx"; +#endif + }; + + uart0: serial@04140000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x04140000 0x0 0x1000>; + clock-frequency = <25000000>; + reg-shift = <2>; + reg-io-width = <4>; + status = "okay"; + }; + + uart1: serial@04150000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x04150000 0x0 0x1000>; + clock-frequency = <25000000>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart2: serial@04160000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x04160000 0x0 0x1000>; + clock-frequency = <25000000>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart3: serial@04170000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x04170000 0x0 0x1000>; + clock-frequency = <25000000>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart4: serial@041C0000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x041C0000 0x0 0x1000>; + clock-frequency = <25000000>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + *** 1925 LINES SKIPPED ***
