The branch main has been updated by olce: URL: https://cgit.FreeBSD.org/src/commit/?id=951788e3733e415ca4721c0a63454937dcb29b2c
commit 951788e3733e415ca4721c0a63454937dcb29b2c Author: Olivier Certner <[email protected]> AuthorDate: 2026-01-27 11:44:29 +0000 Commit: Olivier Certner <[email protected]> CommitDate: 2026-02-11 20:43:21 +0000 hwpstate_amd(4): 'epp' sysctl leaf to operate on real EPP hardware values We were using percents, for compatibility with hwpstate_intel(4), but this looses granularity that might be important in some scenarios or with specific CPU models. For consistency, hwpstate_intel(4) should be changed accordingly, at the expense of breaking compatibility. For release notes: Introduction of hwpstate_amd(4) deserves a release note, even if the original commit was not tagged. Functionality introduced by recent commits tagged with "Relnotes" should be mentioned along that one. PR: 292615 Reviewed by: aokblast Relnotes: yes Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D55009 --- sys/x86/cpufreq/hwpstate_amd.c | 21 ++++++++------------- 1 file changed, 8 insertions(+), 13 deletions(-) diff --git a/sys/x86/cpufreq/hwpstate_amd.c b/sys/x86/cpufreq/hwpstate_amd.c index 18d420dc7747..c35fe0719d74 100644 --- a/sys/x86/cpufreq/hwpstate_amd.c +++ b/sys/x86/cpufreq/hwpstate_amd.c @@ -428,30 +428,25 @@ sysctl_epp_handler(SYSCTL_HANDLER_ARGS) { const u_int max_epp = BITS_VALUE(AMD_CPPC_REQUEST_EPP_BITS, (uint64_t)-1); - const device_t dev = oidp->oid_arg1; + const device_t dev = arg1; struct hwpstate_softc *const sc = device_get_softc(dev); u_int val; - int error = 0; + int error; /* Sysctl knob does not exist if PSTATE_CPPC is not set. */ check_cppc_enabled(sc, __func__); - val = BITS_VALUE(AMD_CPPC_REQUEST_EPP_BITS, sc->cppc.request) * 100 / - max_epp; + val = BITS_VALUE(AMD_CPPC_REQUEST_EPP_BITS, sc->cppc.request); + error = sysctl_handle_int(oidp, &val, 0, req); if (error != 0 || req->newptr == NULL) - goto end; - if (val > 100) { - error = EINVAL; - goto end; - } - val = (val * max_epp) / 100; + return (error); + if (val > max_epp) + return (EINVAL); error = set_cppc_request(dev, BITS_WITH_VALUE(AMD_CPPC_REQUEST_EPP_BITS, val), BITS_WITH_VALUE(AMD_CPPC_REQUEST_EPP_BITS, -1)); - -end: return (error); } @@ -924,7 +919,7 @@ hwpstate_attach(device_t dev) "epp", CTLTYPE_UINT | CTLFLAG_RWTUN | CTLFLAG_MPSAFE, dev, 0, sysctl_epp_handler, "IU", "Efficiency/Performance Preference " - "(range from 0, most performant, through 100, most efficient)"); + "(range from 0, most performant, through 255, most efficient)"); } return (cpufreq_register(dev)); }
