On Thu, 18 Jun 2026, Andrew Turner wrote:
The branch main has been updated by andrew:
URL:
https://cgit.FreeBSD.org/src/commit/?id=c84261da6f6ca6ae6d66eebb86da02467da3dd95
commit c84261da6f6ca6ae6d66eebb86da02467da3dd95
Author: Andrew Turner <[email protected]>
AuthorDate: 2026-06-18 13:30:01 +0000
Commit: Andrew Turner <[email protected]>
CommitDate: 2026-06-18 14:56:53 +0000
arm64: Add an initial GICv5 driver
Add an initial driver for the GICv5 interrupt controller.
This provides host-only support for the GICv5 interrupt controller. It
is specified in the ARM-AES-0070 document & based on version 00eac0.
In the GICv5 there are 3 interrupt spaces: PPI, SPI, and LPI. Unlike
previous interrupt controllers they don't share a single interrupt
ID range, so PPI IRQ 1 and SPI IRQ 1 are different interrupts. There
is a common irqsrc stricture that encodes this information as it is
common across the interrupt types.
Unlike previous GIC versions there are no software generated interrupts
that can target a configurable collection of CPUs. These have been
replaced with LPIs, where each CPU will have one allocated for each
IPI type.
This driver handles the CPU interface and interrupt routing service
(IRS). The CPU interface provides the interface to manage and handle
interrupts, while the IRS handles routing LPIs and SPIs to the target
CPU.
Sponsored by: Arm Ltd
Differential Revision: https://reviews.freebsd.org/D54250
---
sys/arm64/arm64/gicv5.c | 1611 +++++++++++++++++++++++++++++++++++++++++++
sys/arm64/arm64/gicv5_fdt.c | 300 ++++++++
sys/arm64/arm64/gicv5reg.h | 711 +++++++++++++++++++
sys/arm64/arm64/gicv5var.h | 71 ++
sys/conf/files.arm64 | 2 +
5 files changed, 2695 insertions(+)
For what it's worth (or not anymore): arm64 GENERIC-UP fails during make
universe.
--
Bjoern A. Zeeb r15:7
