The branch main has been updated by kbowling: URL: https://cgit.FreeBSD.org/src/commit/?id=fddc393d93169b428fe64e9513ee463b5154b62a
commit fddc393d93169b428fe64e9513ee463b5154b62a Author: Kevin Bowling <[email protected]> AuthorDate: 2026-08-08 11:29:44 +0000 Commit: Kevin Bowling <[email protected]> CommitDate: 2026-08-08 15:46:02 +0000 igb: Match Tx descriptor control to iflib iflib requests transmit completion status only on selected descriptors. Program a zero writeback threshold so igb hardware honors those sparse RS bits instead of writing back every descriptor in threshold-sized batches. Use the existing family specific prefetch threshold: eight descriptors on most controllers and 20 on I354, with a host threshold of one. These values match the Intel-derived Linux and DPDK drivers. Their nonzero writeback settings are not appropriate here because those drivers set RS on every packet. A zero writeback threshold also avoids depending on interrupt timer flushes affected by 82576 specification update erratum 26. Remove the old IGB_TX_WTHRESH macro as well. It has had no callers since the iflib conversion, so its 82575 conditional no longer implements any policy. MFC after: 2 weeks --- sys/dev/e1000/if_em.c | 41 +++++++++++++++++++++++++++++++++-------- sys/dev/e1000/if_em.h | 7 +++---- 2 files changed, 36 insertions(+), 12 deletions(-) diff --git a/sys/dev/e1000/if_em.c b/sys/dev/e1000/if_em.c index b14087f2c88c..b48721a6e5fa 100644 --- a/sys/dev/e1000/if_em.c +++ b/sys/dev/e1000/if_em.c @@ -4205,6 +4205,36 @@ em_legacy_txdctl(struct e1000_hw *hw) return (txdctl); } +static u32 +igb_txdctl(struct e1000_hw *hw) +{ + u32 pthresh; + + switch (hw->mac.type) { + case e1000_i354: + pthresh = I354_TX_PTHRESH; + break; + case e1000_82575: + case e1000_82576: + case e1000_82580: + case e1000_i350: + case e1000_i210: + case e1000_i211: + case e1000_vfadapt: + case e1000_vfadapt_i350: + pthresh = IGB_TX_PTHRESH; + break; + default: + KASSERT(0, ("%s: unsupported MAC type %d", __func__, + hw->mac.type)); + pthresh = IGB_TX_PTHRESH; + break; + } + + return (pthresh | (IGB_TX_HTHRESH << 8) | + E1000_TXDCTL_QUEUE_ENABLE); +} + /********************************************************************* * * Enable transmit unit. @@ -4255,15 +4285,10 @@ em_initialize_transmit_rings(if_ctx_t ctx) E1000_READ_REG(hw, E1000_TDBAL(qid)), E1000_READ_REG(hw, E1000_TDLEN(qid))); - if (hw->mac.type < igb_mac_min) { + if (hw->mac.type < igb_mac_min) txdctl = em_legacy_txdctl(hw); - } else { - txdctl = 0; - txdctl |= 0x1f; /* PTHRESH */ - txdctl |= 1 << 8; /* HTHRESH */ - txdctl |= 1 << 16; /* WTHRESH */ - txdctl |= E1000_TXDCTL_QUEUE_ENABLE; - } + else + txdctl = igb_txdctl(hw); E1000_WRITE_REG(hw, E1000_TXDCTL(qid), txdctl); } diff --git a/sys/dev/e1000/if_em.h b/sys/dev/e1000/if_em.h index 99d4e9d02309..de62c18fac09 100644 --- a/sys/dev/e1000/if_em.h +++ b/sys/dev/e1000/if_em.h @@ -319,10 +319,9 @@ struct igb_vf_mac_filter; #define IGB_RX_WTHRESH ((hw->mac.type == e1000_82576 && \ (sc->intr_type == IFLIB_INTR_MSIX)) ? 1 : 4) -#define IGB_TX_PTHRESH ((hw->mac.type == e1000_i354) ? 20 : 8) -#define IGB_TX_HTHRESH 1 -#define IGB_TX_WTHRESH ((hw->mac.type != e1000_82575 && \ - sc->intr_type == IFLIB_INTR_MSIX) ? 1 : 16) +#define IGB_TX_PTHRESH 8 +#define I354_TX_PTHRESH 20 +#define IGB_TX_HTHRESH 1 /* * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
