JimChengLin commented on PR #2907: URL: https://github.com/apache/brpc/pull/2907#issuecomment-3101394708
> 1. T1 waiter_num + 1 > 2. T1 futex_wait > 3. T2 waiter_num load等于0 如果没有 memory order 限制，是会发生你说的问题。但是 memory order 保证了，你先改了 signal flag 然后又看到 waiter num = 0，那么 T1 一定能在 wait 的时候意识到 signal flag 已经被修改了。多线程就不要思考全局单一顺序了，思考局部顺序就行。 -- This is an automated message from the Apache Git Service. To respond to the message, please log on to GitHub and use the URL above to go to the specific comment. To unsubscribe, e-mail: dev-unsubscr...@brpc.apache.org For queries about this service, please contact Infrastructure at: us...@infra.apache.org --------------------------------------------------------------------- To unsubscribe, e-mail: dev-unsubscr...@brpc.apache.org For additional commands, e-mail: dev-h...@brpc.apache.org
