Felix-Gong commented on code in PR #3332:
URL: https://github.com/apache/brpc/pull/3332#discussion_r3366641534
##########
src/butil/crc32c.cc:
##########
@@ -604,8 +609,195 @@ static bool isZbc() {
}();
return zbc_supported;
}
+
+#if defined(__riscv_zvbc)
+// Hardware-accelerated CRC32C using RISC-V Zvbc vector carry-less
multiplication.
+// Uses RVV vclmul/vclmulh to process 2 lanes per vector operation (VLEN=128).
+// With VLEN=128, each vector register holds 2 x 64-bit elements.
+// 4 lanes are processed using 2 vector register pairs per clmul step.
+static uint32_t rv_crc32c_vclmul(uint32_t crc, const char* buf, size_t len) {
+ crc ^= 0xFFFFFFFF;
+
+ const uint8_t* p = reinterpret_cast<const uint8_t*>(buf);
+ size_t n = len;
+
+ if (n < 64) {
+ return rv_crc32c_bitwise(crc, p, n) ^ 0xFFFFFFFF;
+ }
+
+ // Align to 16-byte boundary
+ uintptr_t mis = (uintptr_t)p & 0xF;
+ if (mis) {
+ size_t pre = 16 - mis;
+ if (pre > n) pre = n;
+ crc = rv_crc32c_bitwise(crc, p, pre);
+ p += pre;
+ n -= pre;
+ if (n < 64) {
+ return rv_crc32c_bitwise(crc, p, n) ^ 0xFFFFFFFF;
+ }
+ }
+
+ // Set up RVV for 64-bit elements: vl = min(VLEN/64, 2) = 2 for VLEN=128
+ size_t vl = __riscv_vsetvl_e64m1(2);
Review Comment:
Fixed. Added a `vl < 2` check after `__riscv_vsetvl_e64m1(2)` that falls
back to the bitwise path if VLEN < 128.
##########
CMakeLists.txt:
##########
@@ -173,7 +173,10 @@ if(CMAKE_CXX_COMPILER_ID STREQUAL "GNU")
elseif((CMAKE_SYSTEM_PROCESSOR MATCHES "riscv64"))
# RISC-V specific optimizations
option(WITH_RISCV_ZBC "Enable RISC-V Zbc carry-less multiplication for
CRC32C acceleration" OFF)
- if(WITH_RISCV_ZBC)
+ option(WITH_RISCV_ZVBC "Enable RISC-V Zvbc vector carry-less
multiplication for CRC32C acceleration" OFF)
+ if(WITH_RISCV_ZVBC)
+ set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -march=rv64gc_zbc_zvbc")
+ elseif(WITH_RISCV_ZBC)
Review Comment:
Fixed. Changed `-march=rv64gc_zbc_zvbc` to `-march=rv64gcv_zbc_zvbc` to
include the base RVV extension.
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