Felix-Gong opened a new pull request, #3374: URL: https://github.com/apache/brpc/pull/3374
## Description `fence.i` is an instruction-synchronization barrier on RISC-V that flushes the instruction cache. Using it in `cpu_relax()` for spin-wait loops is unnecessarily heavy — it should only be used after writing code (e.g., JIT compilation, self-modifying code). ## Fix Replace `fence.i` with `nop` (plus compiler memory barrier). This is consistent with the RISC-V Linux kernel's `cpu_relax()` implementation, which also uses `nop`. ## Verification - Compiled on RISC-V 64-bit server (SG2044, rv64gcv) with GCC 12.3.1 - `libbrpc.a` built successfully - Disassembly confirmed `nop` emitted instead of `fence.i` ## References - [RISC-V Linux kernel cpu_relax](https://github.com/torvalds/linux/blob/master/arch/riscv/include/asm/vdso/processor.h) Signed-off-by: Felix-Gong <[email protected]> -- This is an automated message from the Apache Git Service. To respond to the message, please log on to GitHub and use the URL above to go to the specific comment. To unsubscribe, e-mail: [email protected] For queries about this service, please contact Infrastructure at: [email protected] --------------------------------------------------------------------- To unsubscribe, e-mail: [email protected] For additional commands, e-mail: [email protected]
