From: Miroslaw Walukiewicz <miroslaw.walukiew...@intel.com>

The patch fixes a minor issue with setting up of TSO feature for
ixgbe NICs.

The values for l4_len and tso_segsz was chagned first by txoffload mask
and next set up in the NIC descriptor.

Signed-off-by: Mirek Walukiewicz <miroslaw.walukiewicz at intel.com>
---
 lib/librte_pmd_ixgbe/ixgbe_rxtx.c |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/lib/librte_pmd_ixgbe/ixgbe_rxtx.c 
b/lib/librte_pmd_ixgbe/ixgbe_rxtx.c
index 8559ef6..c9c3104 100644
--- a/lib/librte_pmd_ixgbe/ixgbe_rxtx.c
+++ b/lib/librte_pmd_ixgbe/ixgbe_rxtx.c
@@ -390,13 +390,13 @@ ixgbe_set_xmit_ctx(struct igb_tx_queue* txq,
                type_tucmd_mlhl = IXGBE_ADVTXD_TUCMD_IPV4 |
                        IXGBE_ADVTXD_TUCMD_L4T_TCP |
                        IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
+               mss_l4len_idx |= tx_offload.tso_segsz << IXGBE_ADVTXD_MSS_SHIFT;
+               mss_l4len_idx |= tx_offload.l4_len << IXGBE_ADVTXD_L4LEN_SHIFT;

                tx_offload_mask.l2_len = ~0;
                tx_offload_mask.l3_len = ~0;
                tx_offload_mask.l4_len = ~0;
                tx_offload_mask.tso_segsz = ~0;
-               mss_l4len_idx |= tx_offload.tso_segsz << IXGBE_ADVTXD_MSS_SHIFT;
-               mss_l4len_idx |= tx_offload.l4_len << IXGBE_ADVTXD_L4LEN_SHIFT;
        } else { /* no TSO, check if hardware checksum is needed */
                if (ol_flags & PKT_TX_IP_CKSUM) {
                        type_tucmd_mlhl = IXGBE_ADVTXD_TUCMD_IPV4;

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