03/11/2018 10:34, Honnappa Nagarahalli: > > > > --- > > > > doc/guides/rel_notes/release_18_11.rst | 7 +++++++ > > > > lib/librte_ring/rte_ring_c11_mem.h | 10 ++++------ > > > > 2 files changed, 11 insertions(+), 6 deletions(-) > > > > > > > > diff --git a/doc/guides/rel_notes/release_18_11.rst > > > > b/doc/guides/rel_notes/release_18_11.rst > > > > index 376128f..b68afab 100644 > > > > --- a/doc/guides/rel_notes/release_18_11.rst > > > > +++ b/doc/guides/rel_notes/release_18_11.rst > > > > @@ -69,6 +69,13 @@ New Features > > > > checked out against that dma mask and rejected if out of range. > > > > If more > > > than > > > > one device has addressing limitations, the dma mask is the more > > > restricted one. > > > > > > > > +* **Updated the ring library with C11 memory model.** > > > > + > > > > + Updated the ring library with C11 memory model, in our tests the > > > > + changes decreased latency by 27~29% and 3~15% for MPMC and SPSC > > > cases respectively. > > > > + The real improvements may vary with the number of contending > > > > + lcores and the size of ring. > > > > + > > > Is this a little misleading, and will users expect massive performance > > > improvements generally? The C11 model seems to be used only on some, > > > but not all, arm platforms, and then only with "make" builds. > > > > > > config/arm/meson.build: ['RTE_USE_C11_MEM_MODEL', false]] > This is an error. There is already an agreement that on Arm based platforms, > C11 memory model would be used by default. Specific platforms can override it > if required. > Would this be ab acceptable change for RC2 or RC3?
If NXP and Cavium agrees, I think it can go in RC2. For RC3, not sure.