Hi, The cacheline size (RTE_CACHE_LINE_SIZE) for ARM CPUs is set to be 128B by default. Mellanox's BlueField is an ARM CPU having Cortex-A72 and its CL size is 64B.
I can add config/defconfig_arm64-bluefield-linuxapp-gcc for legacy build anyway. For the meson build, I know it parses the Main ID register to figure out Implementor ID and Part Number. However, Mellanox doesn't program our own ID yet but we set the Part Number as 0xd08 (A72). According to my folks, ARM's A53, A57, A72, and A73 designs all have 64B CL. If that's true, can I push a patch to make the change? Please comment. Thanks, Yongseok
