On Wed, 2019-01-09 at 16:52 +0000, Luca Boccassi wrote: > On Wed, 2019-01-09 at 16:36 +0000, Pavan Nikhilesh Bhagavatula wrote: > > On Wed, 2019-01-09 at 15:41 +0000, Luca Boccassi wrote: > > > External Email > > > > > > --------------------------------------------------------------- > > > ---- > > > --- > > > On Wed, 2019-01-09 at 15:34 +0000, Jerin Jacob Kollanukkaran > > > wrote: > > > > > > Please check below thread and patch. > > > > > > > > > > > > http://mails.dpdk.org/archives/dev/2019-January/122676.html > > > > > > https://patches.dpdk.org/patch/49477/ > > > > > > > > > > > > Debian folks are building like this for the _generic_ > > > > > > image. > > > > > > What ever works for every distros, I am fine with that. > > > > > > > > > > > > meson configure -Dmachine=default > > > > > > meson build > > > > > > cd build > > > > > > ninja > > > > > > ninja install > > > > > > > > > > I think we agree on the idea of having different configs > > > > > for unmodified A72 core and generic build working for all. > > > > > > > > Yes, I agree. config or some scheme to address the generic and > > > > default > > > > usecase. > > > > > > > > > The remaining bits to discuss are: > > > > > - do we want to use the armv8 config for unmodified > > > > > A72? > > > > > - what should be the name of the generic config? > > > > > > > > If all distros following "meson configure -Dmachine=default" > > > > scheme > > > > why not follow that to make generic image. i.e when > > > > machine=default > > > > set then Cache lize size 128B CL specific stuff be kicked in > > > > else > > > > it probe the value based on MIDR from sysfs. > > > > > > > > When we are not cross-compiling can read CTR_EL0[1] register > > (DminLine) to detect the cacheline size based on the native > > machine. > > This method would satisfy all requirements and we need not maintain > > a > > mapping for cacheline_sizes w.r.t part numbers. > > > > > > [1] > > http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.100095_00 > > 01_02_en/way1382037583047.html > > > > (newer kernels expose it as a sysfs entry > > /sys/devices/system/cpu/cpu0/cache/index0/coherency_line_size, we > > can > > use meson run_command to either run a python program with c byte > > code > > or use cc.run('<program>') to get result directly). > > Please, not for the machine=default case - we need a stable, > invariant > option that does not depend on the build worker. > Agreed, Something like :
read_ctr_el0 = ''' #include <stdio.h> int main(int argc, char **argv) { int32_t ctr_el0; __asm__ __volatile__("mrs %0, CTR_EL0\n\t" : "=r" (ctr_el0) : : "memory"); printf("%d\n", 1 << ((ctr_el0 >> 16) & 0xf)); return 0; } ''' if not meson.is_cross_build() and not arm_force_default_march result = cc.run(read_ctr_el0, name : 'cacheline check') if not result.returncode dpdk_conf.set('RTE_CACHE_LINE_SIZE', result. stdout().strip()); else dpdk_conf.set('RTE_CACHE_LINE_SIZE', 128); endif