+ Gavin On Tue, Jan 14, 2020 at 6:09 AM Rasesh Mody <rm...@marvell.com> wrote: > > When handling RX completion queue PMD is not using required read/write > barriers before reading completion queue element (CQE) indices, > updating/writing hardware consumer and producer. > This patch adds appropriate read/write memory barriers in places which > are required by driver and adapter to read or update indices. > > Fixes: 540a211084a7 ("bnx2x: driver core") > Cc: sta...@dpdk.org > > Signed-off-by: Rasesh Mody <rm...@marvell.com> > --- > drivers/net/bnx2x/bnx2x.c | 5 +++++ > drivers/net/bnx2x/bnx2x_rxtx.c | 22 ++++++++++++++++++++++ > 2 files changed, 27 insertions(+) > > diff --git a/drivers/net/bnx2x/bnx2x.c b/drivers/net/bnx2x/bnx2x.c > index ed31335ac..9c5e7995d 100644 > --- a/drivers/net/bnx2x/bnx2x.c > +++ b/drivers/net/bnx2x/bnx2x.c > @@ -1255,6 +1255,11 @@ static uint8_t bnx2x_rxeof(struct bnx2x_softc *sc, > struct bnx2x_fastpath *fp) > return 0; > } > > + /* Add memory barrier as status block fields can change. This memory > + * barrier will flush out all the read/write operations to status > block > + * generated before the barrier. It will ensure stale data is not read > + */ > + mb();
# Do you need full barriers here? # Which architecture did you saw this issue? # rte_cio_* barriers are performance Friday, Have you checked rte_cio_* would suffice the requirements. See the discussion in http://patches.dpdk.org/patch/64038/ I assume 2/3 and 3/3 patches are for the slow path. if so, it is fine to use full barriers on those patches.