To keep order of the modification of RX queue descriptor(rxq->cq_db) and
the CQ doorbell register, a rte_cio_wmb barrier is required.
The situation was rescued by the stronger than required barrier in the
mlx5_uar_write64, it becomes a must when the barrier is relaxed.
Fixes: 6bf10ab69be0 ("net/mlx5: support 32-bit systems")
Cc: [email protected]
Suggested-by: Phil Yang <[email protected]>
Signed-off-by: Gavin Hu <[email protected]>
Reviewed-by: Phil Yang <[email protected]>
---
drivers/net/mlx5/mlx5_rxq.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/net/mlx5/mlx5_rxq.c b/drivers/net/mlx5/mlx5_rxq.c
index dc0fd8211..2d1b153a3 100644
--- a/drivers/net/mlx5/mlx5_rxq.c
+++ b/drivers/net/mlx5/mlx5_rxq.c
@@ -856,7 +856,8 @@ mlx5_arm_cq(struct mlx5_rxq_data *rxq, int sq_n_rxq)
doorbell = (uint64_t)doorbell_hi << 32;
doorbell |= rxq->cqn;
rxq->cq_db[MLX5_CQ_ARM_DB] = rte_cpu_to_be_32(doorbell_hi);
- mlx5_uar_write64(rte_cpu_to_be_64(doorbell),
+ rte_cio_wmb();
+ mlx5_uar_write64_relaxed(rte_cpu_to_be_64(doorbell),
cq_db_reg, rxq->uar_lock_cq);
}
--
2.17.1
