On Mon, Mar 9, 2020 at 10:14 AM Linhaifeng <[email protected]> wrote: > > We nead isb rather than dsb to sync system counter to cntvct_el0.
I'll leave the arm maintainers look at this, but I have a comment on the form. > > Signed-off-by: Haifeng Lin <[email protected]> > --- > lib/librte_eal/common/include/arch/arm/rte_atomic_64.h | 3 +++ > lib/librte_eal/common/include/arch/arm/rte_cycles_64.h | 2 ++ > 2 files changed, 5 insertions(+) > > diff --git a/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h > b/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h > index 859ae129d..705351394 100644 > --- a/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h > +++ b/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h > @@ -21,6 +21,7 @@ extern "C" { > > #define dsb(opt) asm volatile("dsb " #opt : : : "memory") > #define dmb(opt) asm volatile("dmb " #opt : : : "memory") > +#define isb() asm volatile("isb" : : : "memory") dsb and dmb should not be exported as public macros in the first place (I forgot to send the patch that drops those, will send later). Please don't add more public macro that make no sense except for aarch64: neither isb, nor rte_isb. > > #define rte_mb() dsb(sy) > > @@ -186,6 +187,8 @@ rte_atomic128_cmp_exchange(rte_int128_t *dst, > rte_int128_t *exp, > return (old.int128 == expected.int128); > } > > +#define rte_isb() isb() > + > #ifdef __cplusplus > } > #endif -- David Marchand
