> -----Original Message----- > From: Phil Yang <phil.y...@arm.com> > Sent: Monday, February 24, 2020 2:42 PM > To: rsanf...@akamai.com; erik.g.carri...@intel.com; dev@dpdk.org > Cc: david.march...@redhat.com; anatoly.bura...@intel.com; > tho...@monjalon.net; jer...@marvell.com; hemant.agra...@nxp.com; > Honnappa Nagarahalli <honnappa.nagaraha...@arm.com>; Gavin Hu > <gavin...@arm.com>; Phil Yang <phil.y...@arm.com>; nd <n...@arm.com> > Subject: [PATCH 2/2] lib/timer: relax barrier for status update > > Volatile has no ordering semantics. The rte_timer structure defines > timer status as a volatile variable and uses the rte_r/wmb barrier > to guarantee inter-thread visibility. > > This patch optimized the volatile operation with c11 atomic operations > and one-way barrier to save the performance penalty. According to the > timer_perf_autotest benchmarking results, this patch can uplift 10%~16% > timer appending performance, 3%~20% timer resetting performance and 45% > timer callbacks scheduling performance on aarch64 and no loss in > performance for x86. > > Suggested-by: Honnappa Nagarahalli <honnappa.nagaraha...@arm.com> > Signed-off-by: Phil Yang <phil.y...@arm.com> > Reviewed-by: Gavin Hu <gavin...@arm.com> > --- > lib/librte_timer/rte_timer.c | 90 +++++++++++++++++++++++++++++++----
Ping. Thanks, Phil
