On Fri, Oct 8, 2021 at 12:15 PM Bruce Richardson <bruce.richard...@intel.com> wrote: > > On Wed, Oct 06, 2021 at 09:20:08PM +0200, David Marchand wrote: > > Caught while checking CPUID related stuff in OVS. > > > > According to [1], for Structured Extended Feature Flags Enumeration Leaf > > (EAX = 0x07H, ECX = 0): > > > > - BMI1 is associated to EBX, bit 3 (was incorrectly 2), > > - SMEP is associated to EBX, bit 7 (was incorrectly 6), > > - BMI2 is associated to EBX, bit 8 (was incorrectly 7), > > - ERMS is associated to EBX, bit 9 (was incorrectly 8), > > > > This patch then sorts the rest of the extended features (leaf 0) for > > readability. > > > > 1: > > https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf > > > > Fixes: af75078fece3 ("first public release") > > Wow, I'm surprised at it being incorrect this long, but checking the > original commit of code, it does indeed seem true that this is the correct > fixes line! > > > Cc: sta...@dpdk.org > > > > Signed-off-by: David Marchand <david.march...@redhat.com> > > Acked-by: Bruce Richardson <bruce.richard...@intel.com> > > Ideally, I think the fixes should go in a separate patch from the > reordering, but I don't feel strongly about it so this is ok as either one > or two patches IMHO.
I was reading the datasheet and comparing the defines one by one, so easier with sorted defines. Now that I identified the wrong entries, I am fine with splitting since it eases backport on 19.11. I'll send v2 with your ack on both. -- David Marchand
