09/11/2021 05:39, Gagandeep Singh:
> Gagandeep Singh (5):
>   dma/dpaa: introduce DPAA DMA driver
>   dma/dpaa: add device probe and remove functionality
>   dma/dpaa: support basic operations
>   dma/dpaa: support DMA operations
>   dma/dpaa: support statistics

Applied with multiple minor details fixed and dead code removed.

Code changes are below:

diff --git a/MAINTAINERS b/MAINTAINERS
index 0f333b7baa..adee619d36 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1224,6 +1224,12 @@ M: Veerasenareddy Burru <vbu...@marvell.com>
 F: drivers/dma/cnxk/
 F: doc/guides/dmadevs/cnxk.rst
 
+NXP DPAA DMA
+M: Gagandeep Singh <g.si...@nxp.com>
+M: Nipun Gupta <nipun.gu...@nxp.com>
+F: drivers/dma/dpaa/
+F: doc/guides/dmadevs/dpaa.rst
+
 
 RegEx Drivers
 -------------
@@ -1377,17 +1383,6 @@ F: drivers/raw/dpaa2_qdma/
 F: doc/guides/rawdevs/dpaa2_qdma.rst
 
 
-
-Dmadev Drivers
---------------
-
-NXP DPAA DMA
-M: Gagandeep Singh <g.si...@nxp.com>
-M: Nipun Gupta <nipun.gu...@nxp.com>
-F: drivers/dma/dpaa/
-F: doc/guides/dmadevs/dpaa.rst
-
-
 Packet processing
 -----------------
 
diff --git a/doc/guides/dmadevs/dpaa.rst b/doc/guides/dmadevs/dpaa.rst
index 7d51c8c4cd..f99bfc6087 100644
--- a/doc/guides/dmadevs/dpaa.rst
+++ b/doc/guides/dmadevs/dpaa.rst
@@ -2,22 +2,24 @@
     Copyright 2021 NXP
 
 NXP DPAA DMA Driver
-=====================
+===================
 
-The DPAA DMA is an implementation of the dmadev APIs, that provide means
-to initiate a DMA transaction from CPU. The initiated DMA is performed
-without CPU being involved in the actual DMA transaction. This is achieved
-via using the QDMA controller of DPAA SoC.
+The DPAA DMA is an implementation of the dmadev APIs,
+that provide means to initiate a DMA transaction from CPU.
+The initiated DMA is performed without CPU being involved
+in the actual DMA transaction.
+This is achieved via using the QDMA controller of DPAA SoC.
 
-The QDMA controller transfers blocks of data between one source and one
-destination. The blocks of data transferred can be represented in memory
+The QDMA controller transfers blocks of data
+between one source and one destination.
+The blocks of data transferred can be represented in memory
 as contiguous or noncontiguous using scatter/gather table(s).
 
 More information can be found at `NXP Official Website
 
<http://www.nxp.com/products/microcontrollers-and-processors/arm-processors/qoriq-arm-processors:QORIQ-ARM>`_.
 
 Supported DPAA SoCs
---------------------
+-------------------
 
 - LS1046A
 - LS1043A
@@ -35,7 +37,7 @@ See :doc:`../platform/dpaa` for setup information
    dual licensed (BSD & GPLv2), however they are used as BSD in DPDK in 
userspace.
 
 Compilation
-------------
+-----------
 
 For builds using ``meson`` and ``ninja``, the driver will be built when the
 target platform is dpaa-based. No additional compilation steps are necessary.
@@ -57,10 +59,10 @@ The DPAA DMA implements following features in the dmadev 
API:
 - Supports DMA silent mode.
 - Supports issuing DMA of data within memory without hogging CPU while
   performing DMA operation.
-- support statistics
+- Supports statistics.
 
 Platform Requirement
-~~~~~~~~~~~~~~~~~~~~
+--------------------
 
-DPAA DMA driver for DPDK can only work on NXP SoCs as listed in the
-``Supported DPAA SoCs``.
+DPAA DMA driver for DPDK can only work on NXP SoCs
+as listed in the `Supported DPAA SoCs`_.
diff --git a/doc/guides/rel_notes/release_21_11.rst 
b/doc/guides/rel_notes/release_21_11.rst
index ba6ad7bf16..7d60b554d8 100644
--- a/doc/guides/rel_notes/release_21_11.rst
+++ b/doc/guides/rel_notes/release_21_11.rst
@@ -20,9 +20,6 @@ DPDK Release 21.11
       ninja -C build doc
       xdg-open build/doc/guides/html/rel_notes/release_21_11.html
 
-* **Added NXP DPAA DMA driver.**
-
-  * Added a new dmadev driver for NXP DPAA platform.
 
 New Features
 ------------
@@ -99,6 +96,10 @@ New Features
   Added dmadev driver for the DPI DMA hardware accelerator
   of Marvell OCTEONTX2 and OCTEONTX3 family of SoCs.
 
+* **Added NXP DPAA DMA driver.**
+
+  Added a new dmadev driver for NXP DPAA platform.
+
 * **Added support to get all MAC addresses of a device.**
 
   Added ``rte_eth_macaddrs_get`` to allow user to retrieve all Ethernet
diff --git a/drivers/dma/dpaa/dpaa_qdma.c b/drivers/dma/dpaa/dpaa_qdma.c
index cb272c700f..9386fe5698 100644
--- a/drivers/dma/dpaa/dpaa_qdma.c
+++ b/drivers/dma/dpaa/dpaa_qdma.c
@@ -194,7 +194,7 @@ fsl_qdma_pre_request_enqueue_comp_sd_desc(
        struct fsl_qdma_format *csgf_desc;
        int i;
 
-       for (i = 0; i < (int)(queue->n_cq + COMMAND_QUEUE_OVERFLLOW); i++) {
+       for (i = 0; i < (int)(queue->n_cq + COMMAND_QUEUE_OVERFLOW); i++) {
                comp_temp = rte_zmalloc("qdma: comp temp",
                                        sizeof(*comp_temp), 0);
                if (!comp_temp)
diff --git a/drivers/dma/dpaa/dpaa_qdma.h b/drivers/dma/dpaa/dpaa_qdma.h
index bf49b2d5d9..7e9e76e21a 100644
--- a/drivers/dma/dpaa/dpaa_qdma.h
+++ b/drivers/dma/dpaa/dpaa_qdma.h
@@ -22,7 +22,6 @@
 
 #define FSL_QDMA_DMR                   0x0
 #define FSL_QDMA_DSR                   0x4
-#define FSL_QDMA_DEIER                 0xe00
 #define FSL_QDMA_DEDR                  0xe04
 #define FSL_QDMA_DECFDW0R              0xe10
 #define FSL_QDMA_DECFDW1R              0xe14
@@ -47,47 +46,25 @@
 #define FSL_QDMA_BSQMR                 0x800
 #define FSL_QDMA_BSQSR                 0x804
 #define FSL_QDMA_BSQICR                        0x828
-#define FSL_QDMA_CQMR                  0xa00
-#define FSL_QDMA_CQDSCR1               0xa08
-#define FSL_QDMA_CQDSCR2                0xa0c
 #define FSL_QDMA_CQIER                 0xa10
-#define FSL_QDMA_CQEDR                 0xa14
 #define FSL_QDMA_SQCCMR                        0xa20
 
-#define FSL_QDMA_SQICR_ICEN
-
-#define FSL_QDMA_CQIDR_CQT             0xff000000
-#define FSL_QDMA_CQIDR_SQPE            0x800000
-#define FSL_QDMA_CQIDR_SQT             0x8000
-
-#define FSL_QDMA_BCQIER_CQTIE          0x8000
-#define FSL_QDMA_BCQIER_CQPEIE         0x800000
-#define FSL_QDMA_BSQICR_ICEN           0x80000000
-#define FSL_QDMA_BSQICR_ICST(x)                ((x) << 16)
-#define FSL_QDMA_CQIER_MEIE            0x80000000
-#define FSL_QDMA_CQIER_TEIE            0x1
 #define FSL_QDMA_SQCCMR_ENTER_WM       0x200000
 
 #define FSL_QDMA_QUEUE_MAX             8
 
 #define FSL_QDMA_BCQMR_EN              0x80000000
-#define FSL_QDMA_BCQMR_EI              0x40000000
-#define FSL_QDMA_BCQMR_EI_BE           0x40
+#define FSL_QDMA_BCQMR_EI_BE           0x40
 #define FSL_QDMA_BCQMR_CD_THLD(x)      ((x) << 20)
 #define FSL_QDMA_BCQMR_CQ_SIZE(x)      ((x) << 16)
 
-#define FSL_QDMA_BCQSR_QF              0x10000
-#define FSL_QDMA_BCQSR_XOFF            0x1
-#define FSL_QDMA_BCQSR_QF_XOFF_BE      0x1000100
+#define FSL_QDMA_BCQSR_QF_XOFF_BE      0x1000100
 
 #define FSL_QDMA_BSQMR_EN              0x80000000
-#define FSL_QDMA_BSQMR_DI              0x40000000
 #define FSL_QDMA_BSQMR_DI_BE           0x40
 #define FSL_QDMA_BSQMR_CQ_SIZE(x)      ((x) << 16)
 
-#define FSL_QDMA_BSQSR_QE              0x20000
 #define FSL_QDMA_BSQSR_QE_BE           0x200
-#define FSL_QDMA_BSQSR_QF              0x10000
 
 #define FSL_QDMA_DMR_DQD               0x40000000
 #define FSL_QDMA_DSR_DB                        0x80000000
@@ -99,13 +76,9 @@
 #define FSL_QDMA_QUEUE_NUM_MAX         8
 
 #define FSL_QDMA_CMD_RWTTYPE           0x4
-#define FSL_QDMA_CMD_LWC                0x2
+#define FSL_QDMA_CMD_LWC               0x2
 
 #define FSL_QDMA_CMD_RWTTYPE_OFFSET    28
-#define FSL_QDMA_CMD_NS_OFFSET         27
-#define FSL_QDMA_CMD_DQOS_OFFSET       24
-#define FSL_QDMA_CMD_WTHROTL_OFFSET    20
-#define FSL_QDMA_CMD_DSEN_OFFSET       19
 #define FSL_QDMA_CMD_LWC_OFFSET                16
 
 #define QDMA_CCDF_STATUS               20
@@ -115,23 +88,21 @@
 #define QDMA_CCDF_SER                  BIT(30)
 
 #define QDMA_SG_FIN                    BIT(30)
-#define QDMA_SG_EXT                    BIT(31)
 #define QDMA_SG_LEN_MASK               GENMASK(29, 0)
 
-#define QDMA_BIG_ENDIAN                        1
-#define COMP_TIMEOUT                   100000
-#define COMMAND_QUEUE_OVERFLLOW                10
+#define COMMAND_QUEUE_OVERFLOW         10
 
 /* qdma engine attribute */
-#define QDMA_QUEUE_SIZE 64
-#define QDMA_STATUS_SIZE 64
-#define QDMA_CCSR_BASE 0x8380000
-#define VIRT_CHANNELS 32
-#define QDMA_BLOCK_OFFSET 0x10000
-#define QDMA_BLOCKS 4
-#define QDMA_QUEUES 8
-#define QDMA_DELAY 1000
+#define QDMA_QUEUE_SIZE                        64
+#define QDMA_STATUS_SIZE               64
+#define QDMA_CCSR_BASE                 0x8380000
+#define VIRT_CHANNELS                  32
+#define QDMA_BLOCK_OFFSET              0x10000
+#define QDMA_BLOCKS                    4
+#define QDMA_QUEUES                    8
+#define QDMA_DELAY                     1000
 
+#define QDMA_BIG_ENDIAN                        1
 #ifdef QDMA_BIG_ENDIAN
 #define QDMA_IN(addr)          be32_to_cpu(rte_read32(addr))
 #define QDMA_OUT(addr, val)    rte_write32(be32_to_cpu(val), addr)
@@ -180,14 +151,6 @@ struct fsl_qdma_ddf {
        __le32 cmd;
 };
 
-enum dma_status {
-       DMA_COMPLETE,
-       DMA_IN_PROGRESS,
-       DMA_IN_PREPAR,
-       DMA_PAUSED,
-       DMA_ERROR,
-};
-
 struct fsl_qdma_chan {
        struct fsl_qdma_engine  *qdma;
        struct fsl_qdma_queue   *queue;
@@ -195,16 +158,12 @@ struct fsl_qdma_chan {
        struct list_head        list;
 };
 
-struct fsl_qdma_list {
-       struct list_head        dma_list;
-};
-
 struct fsl_qdma_queue {
        struct fsl_qdma_format  *virt_head;
        struct list_head        comp_used;
        struct list_head        comp_free;
        dma_addr_t              bus_addr;
-       u32                     n_cq;
+       u32                     n_cq;
        u32                     id;
        u32                     count;
        u32                     pending;
@@ -214,8 +173,8 @@ struct fsl_qdma_queue {
 };
 
 struct fsl_qdma_comp {
-       dma_addr_t              bus_addr;
-       dma_addr_t              desc_bus_addr;
+       dma_addr_t              bus_addr;
+       dma_addr_t              desc_bus_addr;
        void                    *virt_addr;
        int                     index;
        void                    *desc_virt_addr;
diff --git a/drivers/dma/dpaa/dpaa_qdma_logs.h 
b/drivers/dma/dpaa/dpaa_qdma_logs.h
index 01d4a508fc..762598f8f7 100644
--- a/drivers/dma/dpaa/dpaa_qdma_logs.h
+++ b/drivers/dma/dpaa/dpaa_qdma_logs.h
@@ -5,10 +5,6 @@
 #ifndef __DPAA_QDMA_LOGS_H__
 #define __DPAA_QDMA_LOGS_H__
 
-#ifdef __cplusplus
-extern "C" {
-#endif
-
 extern int dpaa_qdma_logtype;
 
 #define DPAA_QDMA_LOG(level, fmt, args...) \
@@ -39,8 +35,4 @@ extern int dpaa_qdma_logtype;
 #define DPAA_QDMA_DP_WARN(fmt, args...) \
        DPAA_QDMA_DP_LOG(WARNING, fmt, ## args)
 
-#ifdef __cplusplus
-}
-#endif
-
 #endif /* __DPAA_QDMA_LOGS_H__ */
diff --git a/drivers/dma/dpaa/meson.build b/drivers/dma/dpaa/meson.build
index 9ab0862ede..c31a6d91fe 100644
--- a/drivers/dma/dpaa/meson.build
+++ b/drivers/dma/dpaa/meson.build
@@ -2,13 +2,13 @@
 # Copyright 2021 NXP
 
 if not is_linux
-       build = false
-       reason = 'only supported on linux'
+    build = false
+    reason = 'only supported on linux'
 endif
 
 deps += ['dmadev', 'bus_dpaa']
 sources = files('dpaa_qdma.c')
 
 if cc.has_argument('-Wno-pointer-arith')
-       cflags += '-Wno-pointer-arith'
+    cflags += '-Wno-pointer-arith'
 endif
diff --git a/drivers/dma/dpaa/version.map b/drivers/dma/dpaa/version.map
index 7bab7bea48..c2e0723b4c 100644
--- a/drivers/dma/dpaa/version.map
+++ b/drivers/dma/dpaa/version.map
@@ -1,4 +1,3 @@
 DPDK_22 {
-
        local: *;
 };
diff --git a/drivers/dma/meson.build b/drivers/dma/meson.build
index 7cdd6cd28f..8bbc48cbde 100644
--- a/drivers/dma/meson.build
+++ b/drivers/dma/meson.build
@@ -3,7 +3,7 @@
 
 drivers = [
         'cnxk',
-       'dpaa',
+        'dpaa',
         'hisilicon',
         'idxd',
         'ioat',



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