Implement setup functions for the 56G PHY Simics model Signed-off-by: Sergey Temerkhanov <sergey.temerkha...@intel.com> Signed-off-by: Qi Zhang <qi.z.zh...@intel.com> --- drivers/net/ice/base/ice_ptp_hw.c | 29 +++++++++++++++++++++++++++++ drivers/net/ice/base/ice_ptp_hw.h | 2 ++ 2 files changed, 31 insertions(+)
diff --git a/drivers/net/ice/base/ice_ptp_hw.c b/drivers/net/ice/base/ice_ptp_hw.c index 1c5fd799f6..093331331d 100644 --- a/drivers/net/ice/base/ice_ptp_hw.c +++ b/drivers/net/ice/base/ice_ptp_hw.c @@ -1363,6 +1363,35 @@ ice_ptp_read_tx_hwtstamp_status_eth56g(struct ice_hw *hw, u32 *ts_status) return ICE_SUCCESS; } +/** + * ice_ptp_init_phy_cfg - Get the current TX timestamp status + * mask. Returns the mask of ports where TX timestamps are available + * @hw: pointer to the HW struct + */ +enum ice_status +ice_ptp_init_phy_cfg(struct ice_hw *hw) +{ + enum ice_status status; + u32 phy_rev; + + status = ice_read_phy_eth56g_raw_lp(hw, PHY_REG_REVISION, &phy_rev, + true); + if (status) + return status; + + if (phy_rev == PHY_REVISION_ETH56G) { + hw->phy_cfg = ICE_PHY_ETH56G; + return ICE_SUCCESS; + } + + if (ice_is_e810(hw)) + hw->phy_cfg = ICE_PHY_E810; + else + hw->phy_cfg = ICE_PHY_E822; + + return ICE_SUCCESS; +} + /* ---------------------------------------------------------------------------- * E822 family functions * diff --git a/drivers/net/ice/base/ice_ptp_hw.h b/drivers/net/ice/base/ice_ptp_hw.h index a030a9d4ed..1e016ef177 100644 --- a/drivers/net/ice/base/ice_ptp_hw.h +++ b/drivers/net/ice/base/ice_ptp_hw.h @@ -266,6 +266,8 @@ ice_start_phy_timer_eth56g(struct ice_hw *hw, u8 port, bool bypass); enum ice_status ice_phy_cfg_tx_offset_eth56g(struct ice_hw *hw, u8 port); enum ice_status ice_phy_cfg_rx_offset_eth56g(struct ice_hw *hw, u8 port); +enum ice_status ice_ptp_init_phy_cfg(struct ice_hw *hw); + #define PFTSYN_SEM_BYTES 4 #define ICE_PTP_CLOCK_INDEX_0 0x00 -- 2.31.1