Add function to support de-ratematch pre-processing for SW corner cases.
Signed-off-by: Hernan Vargas <hernan.var...@intel.com>
---
drivers/baseband/acc/acc_common.h | 8 ++
drivers/baseband/acc/meson.build | 21 +++++
drivers/baseband/acc/rte_acc100_pmd.c | 108 +++++++++++++++++++++++++-
3 files changed, 134 insertions(+), 3 deletions(-)
diff --git a/drivers/baseband/acc/acc_common.h
b/drivers/baseband/acc/acc_common.h
index 5a9929c336..4b947280c9 100644
--- a/drivers/baseband/acc/acc_common.h
+++ b/drivers/baseband/acc/acc_common.h
@@ -122,6 +122,14 @@
#define ACC_HARQ_ALIGN_64B 64
#define ACC_MAX_ZC 384
+/* De-ratematch code rate limitation when padding is required */
+#define ACC_LIM_03 2 /* 0.03 */
+#define ACC_LIM_09 6 /* 0.09 */
+#define ACC_LIM_14 9 /* 0.14 */
+#define ACC_LIM_21 14 /* 0.21 */
+#define ACC_LIM_31 20 /* 0.31 */
+#define ACC_MAX_E (128 * 1024 - 2)
+
/* Helper macro for logging */
#define rte_acc_log(level, fmt, ...) \
rte_log(RTE_LOG_ ## level, RTE_LOG_NOTICE, fmt "\n", \
diff --git a/drivers/baseband/acc/meson.build b/drivers/baseband/acc/meson.build
index bece3a6e48..b147569d7e 100644
--- a/drivers/baseband/acc/meson.build
+++ b/drivers/baseband/acc/meson.build
@@ -1,6 +1,27 @@
# SPDX-License-Identifier: BSD-3-Clause
# Copyright(c) 2020 Intel Corporation
+# Check for FlexRAN SDK libraries
+dep_dec5g = dependency('flexran_sdk_ldpc_decoder_5gnr', required: false)
+
+if dep_dec5g.found()
+ ext_deps += cc.find_library('libstdc++', required: true)
+ ext_deps += cc.find_library('libirc', required: true)
+ ext_deps += cc.find_library('libimf', required: true)
+ ext_deps += cc.find_library('libipps', required: true)
+ ext_deps += cc.find_library('libsvml', required: true)
+ ext_deps += dep_dec5g
+ ext_deps += dependency('flexran_sdk_ldpc_encoder_5gnr', required: true)
+ ext_deps += dependency('flexran_sdk_LDPC_ratematch_5gnr', required: true)
+ ext_deps += dependency('flexran_sdk_rate_dematching_5gnr', required: true)
+ ext_deps += dependency('flexran_sdk_turbo', required: true)
+ ext_deps += dependency('flexran_sdk_crc', required: true)
+ ext_deps += dependency('flexran_sdk_rate_matching', required: true)
+ ext_deps += dependency('flexran_sdk_common', required: true)
+ cflags += ['-DRTE_BBDEV_SDK_AVX2']
+ cflags += ['-DRTE_BBDEV_SDK_AVX512']
+endif
+
deps += ['bbdev', 'bus_pci']
sources = files('rte_acc100_pmd.c', 'rte_acc200_pmd.c')
diff --git a/drivers/baseband/acc/rte_acc100_pmd.c
b/drivers/baseband/acc/rte_acc100_pmd.c
index f93fd885a3..44fd0e9ad7 100644
--- a/drivers/baseband/acc/rte_acc100_pmd.c
+++ b/drivers/baseband/acc/rte_acc100_pmd.c
@@ -24,6 +24,10 @@
#include "acc100_pmd.h"
#include "acc101_pmd.h"
+#ifdef RTE_BBDEV_SDK_AVX512
+#include <phy_rate_dematching_5gnr.h>
+#endif
+
#ifdef RTE_LIBRTE_BBDEV_DEBUG
RTE_LOG_REGISTER_DEFAULT(acc100_logtype, DEBUG);
#else
@@ -748,6 +752,14 @@ acc100_queue_setup(struct rte_bbdev *dev, uint16_t
queue_id,
ret = -ENOMEM;
goto free_lb_out;
}
+ q->derm_buffer = rte_zmalloc_socket(dev->device->driver->name,
+ RTE_BBDEV_TURBO_MAX_CB_SIZE * 10,
+ RTE_CACHE_LINE_SIZE, conf->socket);
+ if (q->derm_buffer == NULL) {
+ rte_bbdev_log(ERR, "Failed to allocate derm_buffer memory");
+ ret = -ENOMEM;
+ goto free_companion_ring_addr;
+ }
/*
* Software queue ring wraps synchronously with the HW when it reaches
@@ -768,7 +780,7 @@ acc100_queue_setup(struct rte_bbdev *dev, uint16_t queue_id,
q_idx = acc100_find_free_queue_idx(dev, conf);
if (q_idx == -1) {
ret = -EINVAL;
- goto free_companion_ring_addr;
+ goto free_derm_buffer;
}
q->qgrp_id = (q_idx >> ACC100_GRP_ID_SHIFT) & 0xF;
@@ -796,6 +808,9 @@ acc100_queue_setup(struct rte_bbdev *dev, uint16_t queue_id,
dev->data->queues[queue_id].queue_private = q;
return 0;
+free_derm_buffer:
+ rte_free(q->derm_buffer);
+ q->derm_buffer = NULL;
free_companion_ring_addr:
rte_free(q->companion_ring_addr);
q->companion_ring_addr = NULL;
@@ -882,6 +897,7 @@ acc100_queue_release(struct rte_bbdev *dev, uint16_t q_id)
/* Mark the Queue as un-assigned */
d->q_assigned_bit_map[q->qgrp_id] &= (0xFFFFFFFFFFFFFFFF -
(uint64_t) (1 << q->aq_id));
+ rte_free(q->derm_buffer);
rte_free(q->companion_ring_addr);
rte_free(q->lb_in);
rte_free(q->lb_out);
@@ -3102,10 +3118,44 @@ harq_loopback(struct acc_queue *q, struct
rte_bbdev_dec_op *op,
return 1;
}
+/** Assess whether a work around is required for the deRM corner cases */
+static inline bool
+derm_workaround_required(struct rte_bbdev_op_ldpc_dec *ldpc_dec, struct
acc_queue *q)
+{
+ if (!is_acc100(q))
+ return false;
+ int32_t e = ldpc_dec->cb_params.e;
+ int q_m = ldpc_dec->q_m;
+ int z_c = ldpc_dec->z_c;
+ int K = (ldpc_dec->basegraph == 1 ? ACC_K_ZC_1 : ACC_K_ZC_2)
+ * z_c;
+
+ bool required = false;
+ if (ldpc_dec->basegraph == 1) {
+ if ((q_m == 4) && (z_c >= 320) && (e * ACC_LIM_31 > K * 64))
+ required = true;
+ else if ((e * ACC_LIM_21 > K * 64))
+ required = true;
+ } else {
+ if (q_m <= 2) {
+ if ((z_c >= 208) && (e * ACC_LIM_09 > K * 64))
+ required = true;
+ else if ((z_c < 208) && (e * ACC_LIM_03 > K * 64))
+ required = true;
+ } else if (e * ACC_LIM_14 > K * 64)
+ required = true;
+ }
+ if (required)
+ rte_bbdev_log(INFO, "Running deRM pre-processing in SW");
+
+ return required;
+}
+
/** Enqueue one decode operations for ACC100 device in CB mode */
static inline int
enqueue_ldpc_dec_one_op_cb(struct acc_queue *q, struct rte_bbdev_dec_op *op,
- uint16_t total_enqueued_cbs, bool same_op)
+ uint16_t total_enqueued_cbs, bool same_op,
+ struct rte_bbdev_queue_data *q_data)
{
int ret;
if (unlikely(check_bit(op->ldpc_dec.op_flags,
@@ -3163,6 +3213,58 @@ enqueue_ldpc_dec_one_op_cb(struct acc_queue *q, struct
rte_bbdev_dec_op *op,
} else {
struct acc_fcw_ld *fcw;
uint32_t seg_total_left;
+
+ if (derm_workaround_required(&op->ldpc_dec, q)) {
+ #ifdef RTE_BBDEV_SDK_AVX512
+ struct rte_bbdev_op_ldpc_dec *dec = &op->ldpc_dec;
+ struct bblib_rate_dematching_5gnr_request derm_req;
+ struct bblib_rate_dematching_5gnr_response derm_resp;
+ uint8_t *in;
+
+ /* Checking input size is matching with E */
+ if (dec->input.data->data_len < dec->cb_params.e) {
+ rte_bbdev_log(ERR, "deRM: Input size mismatch");
+ return -EFAULT;
+ }
+ /* Run first deRM processing in SW */
+ in = rte_pktmbuf_mtod_offset(dec->input.data, uint8_t
*, in_offset);
+ derm_req.p_in = (int8_t *) in;
+ derm_req.p_harq = (int8_t *) q->derm_buffer;
+ derm_req.base_graph = dec->basegraph;
+ derm_req.zc = dec->z_c;
+ derm_req.ncb = dec->n_cb;
+ derm_req.e = dec->cb_params.e;
+ if (derm_req.e > ACC_MAX_E) {
+ rte_bbdev_log(WARNING,
+ "deRM: E %d > %d max",
+ derm_req.e, ACC_MAX_E);
+ derm_req.e = ACC_MAX_E;
+ }
+ derm_req.k0 = 0; /* Actual output from SDK */
+ derm_req.isretx = false;
+ derm_req.rvid = dec->rv_index;
+ derm_req.modulation_order = dec->q_m;
+ derm_req.start_null_index =
+ (dec->basegraph == 1 ? 22 : 10)
+ * dec->z_c - 2 * dec->z_c
+ - dec->n_filler;
+ derm_req.num_of_null = dec->n_filler;
+ bblib_rate_dematching_5gnr(&derm_req, &derm_resp);
+ /* Force back the HW DeRM */
+ dec->q_m = 1;
+ dec->cb_params.e = dec->n_cb - dec->n_filler;
+ dec->rv_index = 0;
+ rte_memcpy(in, q->derm_buffer, dec->cb_params.e);
+ /* Capture counter when pre-processing is used */
+ q_data->queue_stats.enqueue_warn_count++;
+ #else
+ RTE_SET_USED(q_data);
+ rte_bbdev_log(WARNING,
+ "Corner case may require deRM pre-processing in
SDK"
+ );
+ #endif
+ }
+
fcw = &desc->req.fcw_ld;
q->d->fcw_ld_fill(op, fcw, harq_layout);
@@ -3734,7 +3836,7 @@ acc100_enqueue_ldpc_dec_cb(struct rte_bbdev_queue_data
*q_data,
ops[i]->ldpc_dec.n_cb, ops[i]->ldpc_dec.q_m,
ops[i]->ldpc_dec.n_filler, ops[i]->ldpc_dec.cb_params.e,
same_op);
- ret = enqueue_ldpc_dec_one_op_cb(q, ops[i], i, same_op);
+ ret = enqueue_ldpc_dec_one_op_cb(q, ops[i], i, same_op, q_data);
if (ret < 0) {
acc_enqueue_invalid(q_data);
break;
--
2.37.1
