The default condition in the switch statement in
ice_sched_get_psm_clk_freq() is an unreachable code. The variable
clk_src is restricted to values 0 to 3 with the bit mask and shift
values set.
Fixes: 76ac9d771c97 ("net/ice/base: read PSM clock frequency from register")
Signed-off-by: Vignesh Sridhar <vignesh.srid...@intel.com>
Signed-off-by: Qiming Yang <qiming.y...@intel.com>
---
drivers/net/ice/base/ice_sched.c | 16 ++++++----------
drivers/net/ice/base/ice_sched.h | 5 +++++
2 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/drivers/net/ice/base/ice_sched.c b/drivers/net/ice/base/ice_sched.c
index 83cd152388..f558eccb93 100644
--- a/drivers/net/ice/base/ice_sched.c
+++ b/drivers/net/ice/base/ice_sched.c
@@ -1417,11 +1417,6 @@ void ice_sched_get_psm_clk_freq(struct ice_hw *hw)
clk_src = (val & GLGEN_CLKSTAT_SRC_PSM_CLK_SRC_M) >>
GLGEN_CLKSTAT_SRC_PSM_CLK_SRC_S;
-#define PSM_CLK_SRC_367_MHZ 0x0
-#define PSM_CLK_SRC_416_MHZ 0x1
-#define PSM_CLK_SRC_446_MHZ 0x2
-#define PSM_CLK_SRC_390_MHZ 0x3
-
switch (clk_src) {
case PSM_CLK_SRC_367_MHZ:
hw->psm_clk_freq = ICE_PSM_CLK_367MHZ_IN_HZ;
@@ -1435,11 +1430,12 @@ void ice_sched_get_psm_clk_freq(struct ice_hw *hw)
case PSM_CLK_SRC_390_MHZ:
hw->psm_clk_freq = ICE_PSM_CLK_390MHZ_IN_HZ;
break;
- default:
- ice_debug(hw, ICE_DBG_SCHED, "PSM clk_src unexpected %u\n",
- clk_src);
- /* fall back to a safe default */
- hw->psm_clk_freq = ICE_PSM_CLK_446MHZ_IN_HZ;
+
+ /* default condition is not required as clk_src is restricted
+ * to a 2-bit value from GLGEN_CLKSTAT_SRC_PSM_CLK_SRC_M mask.
+ * The above switch statements cover the possible values of
+ * this variable.
+ */
}
}
diff --git a/drivers/net/ice/base/ice_sched.h b/drivers/net/ice/base/ice_sched.h
index a71619ebf0..c54f5ca9a0 100644
--- a/drivers/net/ice/base/ice_sched.h
+++ b/drivers/net/ice/base/ice_sched.h
@@ -38,6 +38,11 @@
#define ICE_PSM_CLK_446MHZ_IN_HZ 446428571
#define ICE_PSM_CLK_390MHZ_IN_HZ 390625000
+#define PSM_CLK_SRC_367_MHZ 0x0
+#define PSM_CLK_SRC_416_MHZ 0x1
+#define PSM_CLK_SRC_446_MHZ 0x2
+#define PSM_CLK_SRC_390_MHZ 0x3
+
struct rl_profile_params {
u32 bw; /* in Kbps */
u16 rl_multiplier;
--
2.25.1
